Abstract
Properties and sequences allow us to describe complex behaviors in a very compact declarative form. That form is quite different from the procedural style used for writing RTL and other design models as well as test benches. Thus, assertions may also need a different style for debugging them. Issues related to the run time and memory overheads for complex temporal assertions also need to be addressed. The same behavior may be expressed using different assertions. Each may have different efficiency in formal verification and simulation. We discuss both debugging and efficiency in this chapter.
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References
Accellera. Accellera Standard Open Verification Library (OVL) V2.8 (2013)
J. Bergeron, E. Cerny, A. Hunter, A. Nightingale, Verification Methodology Manual for SystemVerilog (Springer, New York, 2006)
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Cerny, E., Dudani, S., Havlicek, J., Korchemny, D. (2015). Debugging Assertions and Efficiency Considerations. In: SVA: The Power of Assertions in SystemVerilog. Springer, Cham. https://doi.org/10.1007/978-3-319-07139-8_19
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DOI: https://doi.org/10.1007/978-3-319-07139-8_19
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Publisher Name: Springer, Cham
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Online ISBN: 978-3-319-07139-8
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