Abstract
This chapter gives an intuitive introduction to SystemVerilog Assertion local variables based on examples. Local variables are a powerful feature of SVA that enable an assertion to capture the value of an expression at a specified point in its evaluation and store that value for later reference or modification. While local variables do not increase the theoretical expressive power of SVA, they do make the encoding of many assertions much easier, and they help to avoid the need to create auxiliary state machines to support assertions.
Local color has a fatal tendency to remain local; but it is also true that the universal often borders on the void. — DuBose Heyward and Hervey Allen
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Notes
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The use of $sampled specifies that sampled values of start and dataIn are used in the always procedure, maintaining consistency with the implicit use of sampled values in a_seq_data_check. See the detailed discussion in Sect. 9.1.1.
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- 3.
A formal tool may also accept procedural concurrent assertions or final assertions.
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The initialization could be skipped because the valid members are of data of type bit, which is initialized by default to 1’b0. The explicit initialization clarifies the intention. The initial values of the activeTag members are not important. Note also that only the first MAX_ACTIVE entries of the array need be initialized.
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© 2015 Springer International Publishing Switzerland
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Cerny, E., Dudani, S., Havlicek, J., Korchemny, D. (2015). An Apology for Local Variables. In: SVA: The Power of Assertions in SystemVerilog. Springer, Cham. https://doi.org/10.1007/978-3-319-07139-8_15
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DOI: https://doi.org/10.1007/978-3-319-07139-8_15
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