Abstract
This chapter covers declaration, scoping, and semantics of reset constructs. SystemVerilog 2009 introduces four new resets, the abort property operators, which come in both synchronous and asynchronous, as well as both passing and failing, flavors. These are in addition to the existing asynchronous disable iff construct at the top-level of a concurrent assertion.
The Metropolis should have been aborted long before it became New York, London or Tokyo.
— John Kenneth Galbraith
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Notes
- 1.
It is presumed that this impulse is a glitch, although, technically, the graphical representation does not imply this without further information, e.g., concerning the timescale. A waveform tool can identify glitches unambiguously.
- 2.
See the Rewriting Algorithms specified in Annex F.4 of the LRM [8].
- 3.
These rules exist in the LRM [8], although they could be relaxed for synchronous aborts.
References
IEEE Std. 1800–2012, IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language (2012)
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© 2015 Springer International Publishing Switzerland
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Cerny, E., Dudani, S., Havlicek, J., Korchemny, D. (2015). Resets. In: SVA: The Power of Assertions in SystemVerilog. Springer, Cham. https://doi.org/10.1007/978-3-319-07139-8_13
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DOI: https://doi.org/10.1007/978-3-319-07139-8_13
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