Abstract
This chapter begins with concluding remarks on the contributions of the book (see Sect. 7.1). We describe our contributions according to the objectives described in the Preface. Section 7.2 describes the future work, which includes verifying DRS designs at runtime.
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References
E. Cetin, O. Diessel, L. Gong, V. Lai, Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration, in International Conference on Field-Programmable Logic and Applications (FPL), Porto, 2013, pp. 1–4
S. Drzevitzky, U. Kastens, M. Platzner, Proof-carrying hardware: towards runtime verification of reconfigurable modules, in International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, 2009, pp. 189–194
W. Luk, N. Shirazi, P.Y. Cheung, Compilation tools for run-time reconfigurable designs, in IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, 1997, pp. 56–65
C. Paiz, C. Pohl, R. Radkowski, J. Hagemeyer, M. Porrmann, U. Ruckert, FPGA-in-the-loop-simulations for dynamically reconfigurable applications, in International Conference on Field-Programmable Technology (FPT), Sydney, 2009, pp. 372–375
K. Paulsson, M. Hubner, M. Jung, J. Becker, Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on Xilinx Virtex-II Pro FPGAs, in IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Karlsruhe, 2006, pp. 1–6
A. Raabe, P.A. Hartmann, J.K. Anlauf, ReChannel: describing and simulating reconfigurable hardware in SystemC. ACM Trans. Des. Autom. Electron. Syst. 13(1), 15:1–15:18 (2008)
I. Robertson, J. Irvine, A design flow for partially reconfigurable hardware. ACM Trans. Embed. Comput. Syst. (TECS) 3(2), 257–283 (2004)
S. Singh, C.J. Lillieroth, Formal verification of reconfigurable cores, in IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, 1999, pp. 25–32
Xilinx Inc., Correcting Single-Event Upsets Through Virtex Partial Configuration (XAPP216) (Xilinx Inc., San Jose, 2000). http://www.xilinx.com/support.html
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Gong, L., Diessel, O. (2015). Conclusions. In: Functional Verification of Dynamically Reconfigurable FPGA-based Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-06838-1_7
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DOI: https://doi.org/10.1007/978-3-319-06838-1_7
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