PSPICE Implementation of Block-Wise Shut-Down Technique for 8 × 8 Bit Low Power Pipelined Booth Multiplier

Abstract

VLSI continues to shrink the feature size of transistors. Nowadays the technology is advancing to deep submicron level in which leakage power becomes dominant in VLSI power consumption. Traditional logic shut-down technique only eliminates dynamic power when circuit is idling, but leakage power cannot be eliminated. To eliminate leakage power, the voltage source (V_dd) should be completely shut down when circuit is idle. However, shutting down and enabling V_dd in a large circuit results in a large transient current, which may lead to error of circuit. Block-wise shut-down technique has been reported by researchers to avoid this issue. It shuts down and recovers back V_dd of blocks in a pipelined circuit sequentially when circuit is idle. This totally eliminates leakage power, while avoiding the large transient current in circuit, hence resulting in less glitches. To verify its effectiveness in power saving, we implemented block-wise logic shut-down in an 8 × 8 pipelined Booth multiplier. Whenever the multiplier is idle, supply voltage is turned off block-by-block, eliminating both dynamic and static power. The schematic of the circuit is designed using PSPICE. Simulation results verify the correct function and the expected shut-down of the designed Booth multiplier. PSPICE power simulation demonstrates effective power saving of the Booth multiplier for the given input pattern sequence.