Instruction Extension and Generation for Adaptive Processors

Abstract

Adaptive reconfigurable instruction-set processors (RISP) is an emerging research field for state-of-the-art VLIW processors. However, it still poses significant challenges to generate and map the original codes to the custom instructions. In this paper we propose an architecture framework to extend new instructions for adaptive RISP. The selected hotspot is considered as a custom instruction and implemented in reconfigurable hardware units. An instruction generator is used to provide a mapping mechanism from hot blocks to hardware implementations, using data flow analysis, instruction clustering, subgraph enumerating and subgraph merging techniques. To demonstrate the effectiveness and performance of the framework and to verify the correctness of the mapping mechanism, a prototype instruction generator has been implemented.