Diffusion-Based Placement Algorithm for Reducing High Interconnect Demand in Congested Regions of FPGAs

Abstract

An FPGA has a finite routing capacity due to which a fair number of highly dense circuits fail to map on a slightly under-resourced architecture. The high-interconnect demand in the congested regions is not met by the available resources as a result of which the circuit becomes un-routable for that particular architecture. In this paper we present a new placement approach which is based on a natural process called Diffusion. Our placer attempts to minimize the routing congestion by evenly disseminating the interconnect demand across an FPGA chip. For the 20 MCNC benchmark circuits, our algorithm reduced the channel width for 6 circuits. The results showed on average 11% reduction in standard deviation of interconnect usage at an expense of an average 5% penalty on wire length. Maximum channel width gain of 17% was also observed.