Abstract
SRAM-based FPGAs have been employed extensively in many applications to implement adaptable systems whose functionalities can be changed at runtime. Unfortunately, even in terrestrial applications the SRAM configuration memory of FPGA devices is highly susceptible to radiation which may cause not only single but also multiple errors in physically adjacent memory cells, called Multiple Bit Upsets (MBUs). This paper proposes a new built-in 3-Dimensional Hamming (3DH) error correcting scheme to mitigate MBUs. The estimations of the probability of occurrence of undetected multiple errors indicate significant improvement of the error correction capabilities of the 3DH scheme proposed here, compared to known 2DH and 1DH schemes. The other important advantage of the new scheme is that it can provide faster reconfiguration of configuration frames affected by multiple errors, because error correction can be done using an internal bus alone.
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References
Altera Corp.: Stratix V Device Handbook. Device Interfaces and Integration. SEU Mitigation for Stratix V Devices, vol. 1, ch. 9. Altera Corp., San Jose (June 2013)
Argyrides, C., et al.: Matrix codes for reliable and cost efficient memory chips. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(3), 420–428 (2011)
Carmichael, C., et al.: Correcting single-event upsets through Virtex partial configuration. Appl. Note XAPP216 (v1.0) (June 1, 2000)
Hsu, C.-L., et al.: High-performance 3D-SRAM architecture design. In: Proc. IEEE Asia Pacific Conf. Circuits and Systems, pp. 907–910 (2010)
Chapman, K.: SEU strategies for Virtex-5 devices. Appl. Note XAPP864 (v2.0) (April 1, 2010)
Kastensmidt, F.L., et al.: Fault-Tolerance Techniques for SRAM-Based FPGAs. Springer, Dordrecht (2006)
Quinn, H., et al.: Radiation-induced multi-bit upsets in SRAM-based FPGAs. IEEE Trans. Nucl. Sci. 52(6), 2455–2461 (2005)
Quinn, H., et al.: Static proton and heavy ion testing of the Xilinx Virtex-5 device. In: Proc. IEEE Workshop on Radiation Effects Data, Honolulu, HI, USA, July 23-27, pp. 177–184 (2007)
Takai, H., et al.: Soft error rate estimations of the Kintex-7 FPGA within the ATLAS Liquid Argon (LAr) Calorimeter. In: TWEPP 2013, Perugia, Italy, September 23-27 (2013)
Lin, S., Costello Jr., D.J.: Error Control Coding: Fundamentals and Applications, 2nd edn. Prentice-Hall, Englewood Cliffs (2004)
Pathak, M., et al.: Reliability and performance-aware 3D SRAM design. In: Proc. IEEE 54th Int. Midwest Symp. Circuits and Systems, pp. 1–4 (2011)
Park, S.P., et al.: Soft-error-resilient FPGAs using built-in 2-D Hamming product code. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(2), 248–256 (2012)
Xilinx, Inc.: Virtex FPGA series configuration and readback. Appl. Note XAPP138 (March 2006)
Xilinx, Inc.: 7 Series FPGAs Configuration: User Guide (October 22, 2013)
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Basha, B.C., Piestrak, S.J., Pillement, S. (2014). Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs. In: Goehringer, D., Santambrogio, M.D., Cardoso, J.M.P., Bertels, K. (eds) Reconfigurable Computing: Architectures, Tools, and Applications. ARC 2014. Lecture Notes in Computer Science, vol 8405. Springer, Cham. https://doi.org/10.1007/978-3-319-05960-0_26
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DOI: https://doi.org/10.1007/978-3-319-05960-0_26
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