Skip to main content

Automated Data Flow Graph Partitioning for a Hierarchical Approach to Wordlength Optimization

  • Conference paper
Reconfigurable Computing: Architectures, Tools, and Applications (ARC 2014)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 8405))

Included in the following conference series:

Abstract

Modern automatic analytical methods for studying range and accuracy in fixed-point systems are gradually replacing the traditional bit-true fixed-point simulations used in Word-Length Optimization (WLO) problems. But these models have several limitations that must be overcome if they are going to be used in real world applications. When targeting large systems, the mathematical expressions quickly become too large to be handled in reasonable times by numerical engines. This paper proposes adapting the classical Fiduccia-Mattheyses partitioning algorithm to the WLO domain to automatically generate hierarchical partitions of the systems to quantize. This is the first time this type of algorithms are used for this purpose. The algorithm has been successfully applied to large problems that could not be addressed before. It generates, in the order of minutes, maneuverable sub-problems where state-of-the-art models can be applied. Thus, scalability is achieved and the impact of the problem size as a constraint is minimized.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Shi, C., Brodersen, R.W.: A perturbation theory on statistical quantization effects in fixed-point DSP with non-stationary inputs. In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, vol. 3, p. III–373. IEEE (2004)

    Google Scholar 

  2. López, J.A., Caffarena, G., Carreras, C., Nieto-Taladriz, O.: Fast and accurate computation of the round-off noise of linear time-invariant systems. IET Circuits, Devices & Systems 2(4), 393 (2008)

    Article  Google Scholar 

  3. Shou, H., Lin, H., Martin, R.R., Wang, G.: Modified affine arithmetic in tensor form for trivariate polynomial evaluation and algebraic surface plotting. Journal of Computational and Applied Mathematics 195(1-2), 155–171 (2006)

    Article  MATH  MathSciNet  Google Scholar 

  4. Parashar, K., Rocher, R., Menard, D., Sentieys, O.: A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems. In: 23rd International Conference on VLSI Design, pp. 318–323. IEEE (2010)

    Google Scholar 

  5. Esteban, L., López, J., Sedano, E., Hernandez-Montero, S., Sanchez, M.: Quantization analysis of the infrared interferometer of the tj-ii stellarator for its optimized fpga-based implementation. IEEE Transactions on Nuclear Science 60, 3592–3596 (2013)

    Article  Google Scholar 

  6. Fiduccia, C., Mattheyses, R.: A linear-time heuristic for improving network partitions. In: 19th Conference on Design Automation, pp. 241–247 (1982)

    Google Scholar 

  7. López, J.A., Sedano, E., Esteban, L., Caffarena, G., Fernández-Herrero, A., Carreras, C.: Applications of Interval-Based Simulations to the Analysis and Design of Digital LTI Systems. In: Cuadrado-Laborde, C. (ed.) Applications of Digital Signal Processing. Number i, 1st edn., pp. 279–296. InTech (2011)

    Google Scholar 

  8. Sarbishei, O., Radecka, K., Zilic, Z.: Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31(3), 343–355 (2012)

    Article  Google Scholar 

  9. Esteban, L., López, J.A., Sedano, E., Sánchez, M.: Quantization Analysis of the Infrared Interferometer of the TJ-II for its Optimized FPGA-based Implementation. In: IEEE 18th Real Time Conference, RTC 2012, Berkeley, California, USA (2012)

    Google Scholar 

  10. Kernighan, B., Lin, S.: An Efficient Heuristic Procedure for Partitioning Graphs. The Bell System Technical Journal 49(1), 291–307 (1970)

    Article  MATH  Google Scholar 

  11. Hall, K.M.: An r-Dimensional Quadratic Placement Algorithm. Management Science 17(3), 219–229 (1970)

    Article  MATH  Google Scholar 

  12. Tsay, R.S., Kuh, E.: A unified approach to partitioning and placement (VLSI layout). IEEE Transactions on Circuits and Systems 38(5), 521–533 (1991)

    Article  Google Scholar 

  13. Bui, T.N., Moon, B.R.: Genetic algorithm and graph partitioning. IEEE Transactions on Computers 45(7), 841–855 (1996)

    Article  MATH  MathSciNet  Google Scholar 

  14. Johnson, E.L., Mehrotra, A., Nemhauser, G.L.: Min-cut clustering. Mathematical Programming 62, 133–151 (1993)

    Article  MATH  MathSciNet  Google Scholar 

  15. Alpert, C.J., Kahng, A.B.: Recent directions in netlist partitioning: a survey. The VLSI Journal on Integration 19(1-2), 1–81 (1995)

    Article  MATH  Google Scholar 

  16. Kim, J., Hwang, I., Kim, Y.H., Moon, B.R.: Genetic approaches for graph partitioning: a survey. In: Proceedings of the 13th Annual Conference on Genetic and Evolutionary Computation, pp. 473–480. ACM (2011)

    Google Scholar 

  17. Krishnamurthy, B.: An Improved Min-Cut Algonthm for Partitioning VLSI Networks. IEEE Transactions on Computers C-33(5), 438–446 (1984)

    Article  MathSciNet  Google Scholar 

  18. Sanchis, L.: Multiple-way network partitioning with different cost functions. IEEE Transactions on Computers 42(12), 1500–1504 (1993)

    Article  Google Scholar 

  19. Johnson, D.S., Aragon, C.R., McGeoch, L.A., Schevon, C.: Optimization by Simulated Annealing: An Experimental Evaluation; Part I, Graph Partitioning. Operations Research 37(6), 865–892 (1989)

    Article  MATH  Google Scholar 

  20. Berge, C.: Graphs and Hypergraphs. Elsevier (1976)

    Google Scholar 

  21. Mathews, V.J., Sicuranza, G.L.: Polynomial Signal Processing. Wiley (2000)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2014 Springer International Publishing Switzerland

About this paper

Cite this paper

Sedano, E., Menard, D., López, J.A. (2014). Automated Data Flow Graph Partitioning for a Hierarchical Approach to Wordlength Optimization. In: Goehringer, D., Santambrogio, M.D., Cardoso, J.M.P., Bertels, K. (eds) Reconfigurable Computing: Architectures, Tools, and Applications. ARC 2014. Lecture Notes in Computer Science, vol 8405. Springer, Cham. https://doi.org/10.1007/978-3-319-05960-0_12

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-05960-0_12

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-05959-4

  • Online ISBN: 978-3-319-05960-0

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics