Abstract
In this paper we describe and evaluate two possible architectures using 3D DRAMs and PCMs in the processor memory hierarchy. We explore using (a) 3D DRAM as main memory with PCM as backing store and (b) 3D DRAM as the Last Level Cache and PCM as the main memory. In each of these configurations, since the proposed main memories are significantly faster than today’s off-chip 2D DRAMs for main memory and either flash memory based SSDs or magnetic hard drives for secondary storage, we will introduce hardware assistance for virtual to physical address translation and to speed up page-fault handling.
We use Simics, a full system simulator and benchmarks from both SPEC 2006 and OLTP suites to evaluate our designs. Our experiments measure energy consumed and execution performance; we use CACTI for obtaining energy and latency values for our memory configurations.
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References
Qureshi, M., Gurumurthi, S., Rajendran, B.: Phase Change Memory – from Devices to Systems. M. & C. Publishers, Morgan & Claypool Publishers (2011)
Qureshi, M., Srinivasan, V., Rivers, J.A.: Scalable high performance main memory system using phase change memory tecnology. In: Proceedings of ISCA 2009, pp. 24–33 (2009)
Qureshi, M.: Improving read performance of phase change memories via write cancellation and write pausing. In: Proceedings of HPCA 2010, pp. 1–11 (2010)
Quereshi, M., Franceschini, M., Jagmohan, A., Lastras, L.: PreSET: Improving performance of phase change memories by exploiting asymmetry in write times. In: ISCA 2012, pp. 380–391 (2012)
Wulf, W.A., McKee, S.A.: Hitting the Memory Wall: Implications of the Obvious. Computer Architecture News 23(1), 20–24 (1995)
Lau, J.: Through-Silicon Vias for 3D Integration. McGraw-Hill Professional (2012)
Lecarpentier, G., Vos, J.D.: Die 2 Die Bonding, SET S.A.S. (Smart Equipment Technology), 131 Impasse Barteudet, 74490 Saint Jeoire, France & IMEC, Kapeldreef 75, Leuven B-3001, Belgium (2012)
Loh, G.: Computer architecture for Die Stacking. In: International Symposium on VLSI Technology, Systems and Applications, pp. 1–2, Hsinchu, Taiwan (2012)
Liu, C.: Bridging the processor-memory gap with 3D IC technology. IEEE Design and Test, 564–565 (2005)
Sun, H.: 3D DRAM design and application to 3D multicore systems. IEEE Design & Test of Computers, 36–46 (2009)
Weis, C.: Design space exploration for 3D-stacked DRAMs. In: Proceedings of DATE-11 (2001)
Loh, G.: 3D-Stacked Memory Architectures for Multi-core Processors. In: 35th International Symposium on Computer Architecture, ISCA 2008, pp. 453–464 (2008)
Lee, B.C., Ipek, E., Mutlu, O., Burger, D.: Architecting phase change memory as a scalable dram alternative. Sigarc Comput. Archit. News 3(37), 2–13 (2009)
Barr, T., Cox, A., Rixner, S.: Translation caching: skip, don’t walk (the page table). In: ISCA 2010, Saint-Melo, pp. 48–59 (2010)
Wilton, S.J.E., Jouppi, N.: CACTI: an enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits 31(5), 677–688 (1996)
Sherman, J., Kavi, K., Potter, B., Ignatowski, M.: A Multi-core Memory Organization for 3-D DRAM as Main Memory. In: Kubátová, H., Hochberger, C., Daněk, M., Sick, B. (eds.) ARCS 2013. LNCS, vol. 7767, pp. 62–73. Springer, Heidelberg (2013)
Xiangyu, D., Cong, X., Yuan, X., Norman, P.J.: NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31(7), 994–1007 (2012)
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Kavi, K., Pianelli, S., Pisano, G., Regina, G., Ignatowski, M. (2014). 3D DRAM and PCMs in Processor Memory Hierarchy. In: Maehle, E., Römer, K., Karl, W., Tovar, E. (eds) Architecture of Computing Systems – ARCS 2014. ARCS 2014. Lecture Notes in Computer Science, vol 8350. Springer, Cham. https://doi.org/10.1007/978-3-319-04891-8_16
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DOI: https://doi.org/10.1007/978-3-319-04891-8_16
Publisher Name: Springer, Cham
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