Abstract
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Lecture on concurrent deserializer lab
This brief lecture merely introduces the lab, which includes simulation and synthesis, the latter primarily as a verification tool.
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Lab
We debug our first-draft Deserializer and make many small changes to modify the memory so it will operate as a dual-port. We change our FIFO state machine so it can take advantage of the dual-port memory.
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Lab Postmortem
We stop for Q&A and discuss a few verilog debugging techniques.
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© 2014 Springer International Publishing Switzerland
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Williams, J.M. (2014). Chapter 20 Week 10 Class 1. In: Digital VLSI Design with Verilog. Springer, Cham. https://doi.org/10.1007/978-3-319-04789-8_20
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DOI: https://doi.org/10.1007/978-3-319-04789-8_20
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Online ISBN: 978-3-319-04789-8
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