Chapter 18 Week 9 Class 1

Abstract

• Lecture on timing checks and pulse controls

  Topics: Relation to assertions, the twelve verilog timing checks, pulse filtering and delay pessimism.

  Summary: This will complete our study of timing issues in verilog, as well as of the allowed contents of a specify block. We start by discussing the relationships among timing checks, assertions, and system tasks. After introducing the time-stamp/time-check rationale, we present the 12 timing checks and their default arguments. After describing conditioned events and timing-check notifiers, we explain verilog simulator pulse handling, inertial delay, the PATHPULSE task, and pessimism reduction in the specify block.

• Lab on timing checks

  We exercise the timing checks and pulse-filtering features of specify blocks.

• Lab Postmortem

  We entertain a Q&A session only, this time.