Abstract
Lecture on UDP’s, timing triplets, and switch-level models
Topics: User-defined primitives, timing triplets, switch-level primitives and nets, trireg nets.
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© 2014 Springer International Publishing Switzerland
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Williams, J.M. (2014). Chapter 15 Week 7 Class 2. In: Digital VLSI Design with Verilog. Springer, Cham. https://doi.org/10.1007/978-3-319-04789-8_15
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DOI: https://doi.org/10.1007/978-3-319-04789-8_15
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Publisher Name: Springer, Cham
Print ISBN: 978-3-319-04788-1
Online ISBN: 978-3-319-04789-8
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