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Hardware Reduction in Logic Circuits of Moore FSM

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Synthesis and Optimization of FPGA-Based Systems

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 294))

Abstract

The Chapter is devoted to the problems of optimization of Moore FSM logic circuits implemented with FPGAs. The general characteristic is given for methods of functional and structural decomposition. Distinctive features of FPGA are analyzed allowing the number of look-up table (LUT) elements in logic circuits of Moore FSMs to be decreased. The classification of optimization methods are given for Moore FSM including: (1) the transformation of state codes into codes of the classes of pseudoequivalent states (PES); (2) presentation of state codes as concatenations of codes of PES and collections of microoperations; (3) replacement of logical conditions (input variables of FSM) by additional variables. All discussed methods are illustrated by examples. The chapter is written together with PhD student Olena Hebda (University of Zielona Gora, Poland).

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Authors and Affiliations

  1. Department of Electronics, Telecommunications and Informatics, University of Aveiro, Aveiro, Portugal

    Valery Sklyarov & Iouliia Skliarova

  2. Institute of Informatics and Electronics, University of Zielona Gora, Zielona Gora, Poland

    Alexander Barkalov & Larysa Titarenko

Authors
  1. Valery Sklyarov
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  2. Iouliia Skliarova
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  3. Alexander Barkalov
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  4. Larysa Titarenko
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Correspondence to Valery Sklyarov .

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Sklyarov, V., Skliarova, I., Barkalov, A., Titarenko, L. (2014). Hardware Reduction in Logic Circuits of Moore FSM. In: Synthesis and Optimization of FPGA-Based Systems. Lecture Notes in Electrical Engineering, vol 294. Springer, Cham. https://doi.org/10.1007/978-3-319-04708-9_6

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  • DOI: https://doi.org/10.1007/978-3-319-04708-9_6

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-04707-2

  • Online ISBN: 978-3-319-04708-9

  • eBook Packages: EngineeringEngineering (R0)

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