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Continuous-Time Digital Design Techniques

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Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

Abstract

Designing continuous-time digital circuits requires a design flow that is radically different from traditional, discrete-time digital design, which is usually based on hardware description languages (HDLs) and standard cells. In some aspects, continuous-time digital design is closer to analog design than to digital. However, since two-level signals are mostly used, most building blocks are digital gates, so that many digital design aspects are important as well. This chapter discusses the fundamentals of continuous-time digital design. It starts by motivating the use of continuoustime circuits in this work and discussing their advantages and disadvantages. Next, the basic concepts in continuoustime digital design are introduced using the most basic continuoustime circuit, the delay line. After treating delay lines, some other important lowlevel building blocks for continuoustime digital systems are presented, and finally a design flow for this type of systems is proposed

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Notes

  1. 1.

    While \(RC\) is often used as a metric for delay, it is not necessarily equal to the unit delay \(\tau _u\), which was defined in Sect. 4.3.1: \(RC\) is the time needed to reach a voltage \(V_{\mathrm {dd}}/e\) after the input switches infinitely fast from \(V_{\mathrm {dd}}\) to 0, or to reach \(V_{\mathrm {dd}} (1-1/e)\) after the input switches from 0 to \(V_{\mathrm {dd}}\). On the other hand, \(\tau _u\) is the time needed for the output to cross \(V_{\mathrm {dd}}/2\) after the input has crossed \(V_{\mathrm {dd}}/2\). The ratio between both delay metrics depends on the signal edge shapes. However, both metrics are proportional to each other and in the same order of magnitude.

  2. 2.

    The name Vernier refers to the Vernier scale, which applies a similar principle to measure distances and was invented by Pierre Vernier in 1631 [46].

  3. 3.

    Except for possible increased delay due to a higher capacitive load. This issue is treated in more detail in Chaps. 5 and 6.

  4. 4.

    SPICE is only one of several similar transistor-level simulators, and furthermore many different open-source and commercial implementations of SPICE exist. The simulations performed in this work can be run with any of those simulators. In this work, HSpice [16] was used for many simulations.

References

  1. Baron RG (1957) The Vernier time-measuring technique. Proc IRE 45(1):21–30. doi:10.1109/JRPROC.1957.278252

    Article  MathSciNet  Google Scholar 

  2. Betancourt-Zamora RJ, Lee TH (1998) Low phase noise CMOS ring oscillator VCOs for frequency synthesis. In: International workshop on design of mixed-mode integrated circuits, pp 37–40

    Google Scholar 

  3. Calibre (2010) Calibre interactive version 2010.3\_37.26. Mentor Graphics Corporation

    Google Scholar 

  4. Chen P, Chen PY, Lai JS, Chen YJ (2010) FPGA Vernier digital-to-time converter with 1.58 ps resolution and 59.3 minutes operation range. IEEE Trans Circ Syst Part I: Regular Papers 57(6):1134–1142

    Google Scholar 

  5. Cooley JW, Tukey JW (1965) An algorithm for the machine calculation of complex Fourier series. AMS Mathematics of Computation 19(90):297–301

    Article  MATH  MathSciNet  Google Scholar 

  6. Dally WJ, Poulton JW (1998) Digital Systems Engineering. ISBN: 0-521-59292-5, Cambridge University Press.

    Google Scholar 

  7. Daniels J (2008) sig Toolbox (Matlab).

    Google Scholar 

  8. Daniels J (2010) Mat2Spice Toolbox (Matlab), version 2.

    Google Scholar 

  9. Daniels J (2011) Time-based analog-to-digital converters for broadband communication applications. PhD thesis, KU Leuven, Belgium.

    Google Scholar 

  10. Daniels J, Dehaene W, Steyaert M, Wiesbauer A (2008a) A 350-MHz combined TDC-DTC with 61 ps resolution for asynchronous \(\Delta \Sigma \) ADC applications. In: IEEE Asian Solid-State Circuits Conference (ASSCC), pp 365–368.

    Google Scholar 

  11. Daniels J, Dehaene W, Steyaert M, Wiesbauer A (2008b) A/D conversion using an asynchronous delta-sigma modulator and a time-to-digital converter. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp 1648–1651.

    Google Scholar 

  12. Daniels J, Dehaene W, Steyaert MSJ, Wiesbauer A (2010) A/D conversion using asynchronous delta-sigma modulation and time-to-digital conversion. IEEE Transactions on Circuits and Systems–Part I: Regular Papers 57(9):2404–2412.

    Google Scholar 

  13. Dudek P, Szczepański S, Hatfield JV (2000) A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. IEEE Journal of Solid-State Circuits 35(2):240–247

    Article  Google Scholar 

  14. Gnecchi S (2012) Design of a digital-to-time converter for GHz-range pulse width and position modulation (PWPM). Master’s thesis, KU Leuven, Belgium

    Google Scholar 

  15. Henzler S, Koeppe S, Lorenz D, Kamp W, Kuenemund R, Schmitt-Landsiedel D (2008) A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion. IEEE Journal of Solid-State Circuits 43(7):1666–1676

    Article  Google Scholar 

  16. HSPICE (2010) HSPICE Version D-2010.03-SP2. Synopsys Inc.

    Google Scholar 

  17. Jansson JP, Mäntyniemi A, Kostamovaara J (2006) A CMOS time-to-digital converter with better than 10 ps single-shot precision. IEEE Journal of Solid-State Circuits 41(6):1286–1296. doi:10.1109/JSSC.2006.874281

    Article  Google Scholar 

  18. Lin SY, Liu SI (2009) A 1.5 GHz all-digital spread-spectrum clock generator. IEEE Journal of Solid-State Circuits 44(11):3111–3119

    Article  Google Scholar 

  19. Maneatis JG (1996) Low-jitter and process-independent DLL and PLL based on self-biased techniques. IEEE Journal of Solid-State Circuits 31(11):1723–1732

    Article  Google Scholar 

  20. Maneatis JG, Horowitz MA (1993) Precise delay generation using coupled oscillators. IEEE Journal of Solid-State Circuits 28(12):1273–1282

    Article  Google Scholar 

  21. Matlab (2011) Matlab 7.13.0.564 (R2011b). The MathWorks Inc.

    Google Scholar 

  22. Michielsen S (2011) Picoseconde accurate tijdsreproductie. Master’s thesis, KU Leuven, Belgium

    Google Scholar 

  23. Mota M, Christiansen J (1999) A high-resolution time interpolator based on a delay locked loop and an \(RC\) delay line. IEEE J Solid-State Circ 34(10):1360–1366

    Article  Google Scholar 

  24. Nagel LW (1975) SPICE2: a computer program to simulate semiconductor circuits. Memorandum no. ERL-M520, University of California, Berkeley

    Google Scholar 

  25. Nagel LW, Pederson DO (1973) SPICE (Simulation Program with Integrated Circuit Emphasis). Memorandum no. ERL-M382, University of California, Berkeley

    Google Scholar 

  26. Nuyts PAJ, Rooseleer B (2008) Een sigma-delta analoog-digitaal-convertor met een time-to-digital-convertor als booster. Master’s thesis, KU Leuven, Belgium

    Google Scholar 

  27. Nuyts PAJ, Singerl P, Dielacher F, Reynaert P, Dehaene W (2010) A fully digital GHz-range multimode transmitter front-end based on locked delay lines. In: European Reconfigurable Radio Technologies Workshop (ERRT), pp 126–128

    Google Scholar 

  28. Nuyts PAJ, Singerl P, Dielacher F, Reynaert P, Dehaene W (2011) A fully digital delay-line based GHz-range multimode transmitter front-end in 65-nm CMOS. In: IEEE European Solid-State Circuits Conference (ESSCIRC), pp 395–398

    Google Scholar 

  29. Nuyts PAJ, Singerl P, Dielacher F, Reynaert P, Dehaene W (2012) A fully digital delay line based GHz range multimode transmitter front-end in 65-nm CMOS. IEEE J Solid-State Circ 47(7):1681–1692

    Article  Google Scholar 

  30. Nuyts PAJ, Redant T, Michielsen S, Reynaert P, Dehaene W (2013a) Topology selection for high-precision Vernier digital-to-time converters in standard CMOS. Elsevier Int J Electron Commun (AEÜ) 67(4):355–360

    Article  Google Scholar 

  31. Nuyts PAJ, Reynaert P, Dehaene W (2013b) A fully digital PWM-based 1 to 3 GHz multistandard transmitter in 40-nm CMOS. In: IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp 419–422

    Google Scholar 

  32. Park M, Perrott MH, Staszewski RB (2011) An amplitude resolution improvement of an RF-DAC employing pulsewidth modulation. IEEE Trans Circ Syst I Regul Pap 58(11):2590–2603

    Google Scholar 

  33. Pelgrom MJM, Duinmaijer ACJ, Welbers APG (1989) Matching properties of MOS transistors. IEEE J Solid-State Circ 24(5):1433–1440

    Article  Google Scholar 

  34. Rabaey JM, Chandrakasan A, Nikolić B (2003) Digital integrated circuits - a design perspective, 2nd edn. Prentice Hall. Upper Saddle River, New Jersey, USA ISBN: 0-13-120764-4

    Google Scholar 

  35. Rahkonen TE, Kostamovaara JT (Aug1993) The use of stabilized CMOS delay lines for the digitization of short time intervals. IEEE J Solid-State Circ 28(8):887–894. doi:10.1109/4.231325

    Article  Google Scholar 

  36. Ramakrishnan V, Balsara PT (2006) A wide-range, high-resolution, compact, CMOS time to digital converter. In: IEEE international conference on VLSI design

    Google Scholar 

  37. Redant T, Daniels J, Steyaert MSJ, Dehaene W (2011a) Multiple event time-to-digital conversion-based pulse digitization for a 250 MHz pulse radio ranging application. IEEE Trans Circ Syst I Regul Pap 58(11):2614–2622

    Google Scholar 

  38. Redant T, Stubbe F, Dehaene W (2011b) A low power time-of-arrival ranging front end based on a 8-channel 2.2mW, 53ps single-shot-precision time-to-digital converter. In: IEEE Asian Solid-State Circuits Conference (ASSCC), pp 321–324

    Google Scholar 

  39. Staszewski RB, Muhammad K, Leipold D, Hung CM, Ho YC, Wallberg JL, Fernando C, Maggio K, Staszewski R, Jung T, Koh J, John S, Deng IY, Sarda V, Moreira-Tamayo O, Mayega V, Katz R, Friedman O, Eliezer OE, de Obaldia E, Balsara PT (2004) All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS. IEEE J Solid-State Circ 39(12):2278–2291

    Article  Google Scholar 

  40. Staszewski RB, Wallberg JL, Rezeq S, Hung CM, Eliezer OE, Vamulapalli SK, Fernando C, Maggio K, Staszewski R, Barton N, Lee MC, Cruise P, Entezari M, Muhammad K, Leipold D (2005) All-digital PLL and transmitter for mobile phones. IEEE J Solid-State Circ 40(12):2469–2482

    Article  Google Scholar 

  41. Staszewski RB, Vemulapalli S, Vallur P, Wallberg J, Balsara PT (2006) 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS. IEEE Trans Circ Syst II Express Briefs 53(3):220–224

    Google Scholar 

  42. Straayer MZ, Perrott MH (2009) A multi-path gated ring oscillator TDC with first-order noise shaping. IEEE J Solid-State Circ 44(4):1089–1098

    Article  Google Scholar 

  43. Toifl T, Vari R, Moreira P, Marchioro A (1999) 4-channel rad-hard delay generation ASIC with 1ns timing resolution for LJC. IEEE Trans Nucl Sci 46(3):139–143

    Article  Google Scholar 

  44. Wikipedia, Cooley-Tukey FFT algorithm. http://en.wikipedia.org/wiki/Cooley-Tukey_FFT_algorithm

  45. Wikipedia, SPICE. http://en.wikipedia.org/wiki/SPICE

  46. Wikipedia, Vernier scale. http://en.wikipedia.org/wiki/Vernier_scale

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Acknowledgments

The authors wish to acknowledge Tom Redant for his contribution in the derivation of the results presented in Sect. 4.6.3.2

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Authors and Affiliations

  1. Tri ICT, Zaventem, Belgium

    Pieter A. J. Nuyts

  2. ESAT-MICAS, KU Leuven, Leuven, Belgium

    Pieter A. J. Nuyts, Patrick Reynaert & Wim Dehaene

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  1. Pieter A. J. Nuyts
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  3. Wim Dehaene
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Correspondence to Pieter A. J. Nuyts .

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Nuyts, P.A.J., Reynaert, P., Dehaene, W. (2014). Continuous-Time Digital Design Techniques. In: Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-03925-1_4

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  • DOI: https://doi.org/10.1007/978-3-319-03925-1_4

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