An All Digital Phase Locked Loop (ADPLL) is an alternative to a traditional Phase Locked Loop (PLL) for implementation in nanoscale digital CMOS, especially as part of a system-on-chip (SoC) [1, 2]. One of the key advantages of ADPLLs over their analog counterparts is that they remove the need for large capacitors within the loop filter by utilizing digital circuits to achieve the desired filtering function. The resulting area savings are important for achieving a low-cost solution. Moreover, the phase error signal in an ADPLL is a digital word that is produced by means of digital circuits such as accumulators, samplers and Time-to-Digital Converters [3, 4]. As a consequence, a much more attractive, mostly digital, design flow is achieved [2]. Furthermore, the essentially digital architecture of an ADPLL can be augmented with reconfigurable gains and a filter [5, 6], or with a software-assisted digital processor for calibration [7].

In the literature of recent years, there has been a significant effort to improve the performance of ADPLLs in terms of the output frequency [6, 8], resolution [9], bandwidth [10–12], locking speed [13, 14], phase noise [15–17], and power consumption [18].

In this book, we focus on ADPLLs that include TDCs with noise-shaping of the quantization error. We explain how to design an ADPLL, analyse its noise performance and realize behavioral models that require the minimum possible simulation time. We also review the main TDC architectures in order to highlight the advantages of a first-order noise-shaping TDC. We show how to relate the operation of a TDC to a quantizer and/or a first-order sigma-delta modulator. Furthermore, we determine analytically the precisions of a quantizer and a sigma-delta modulator when followed by a moving average filter in terms of the maximum difference between the input and the output when this difference is bounded.

First-order noise-shaping of the quantization error is produced by a system that can be represented by a first-order sigma-delta modulator. During our analysis, we show that there is an inherent sigma-delta modulation in both Vernier TDCs and accumulator-based ADPLLs. In fact, we demonstrate that the models of a Vernier TDC and an accumulator-based ADPLL can be based on sigma-delta modulators. In particular, we use the equations of a sigma-delta modulator to implement an efficient model of an accumulator-based ADPLL.

The book is organized as follows:

In Chap. 2, we review the operating principles of the main topologies of ADPLLs (PFD-plus-TDC-based, TDC-based and accumulator-based ADPLLs) in terms of the integer and fractional parts of the phase difference. We also mention the flip-flop-based ADPLL which can be considered as a special case of a TDC-based ADPLL. We show models that describe the phase-to-digital conversion in each ADPLL architecture. We also discuss possible strategies to clock the digital filter in the various ADPLL architectures. We show how to modify the ADPLL architectures to synthesize a fractional ratio between the frequencies of the reference oscillator and the DCO. Finally, we compare the ADPLL architectures in terms of phase-to-digital conversion, TDC dynamic range, and metastability. The analytical approach used in this chapter is general and it can be extended to any modified ADPLL architecture that can be obtained from those we have studied.

In Chap. 3, we briefly review the main TDC architectures that have been published in the literature. We introduce notation for comparing different TDC architectures in terms of their operating principles and time resolution. By comparing different TDC architectures, we show that a first-order noise-shaping TDC is an interesting architecture for digital systems because it allows a tradeoff between high time resolution and speed. We also show how the Vernier method can be considered as a special case of sigma-delta modulation. To our knowledge, the Vernier method is recognized as a particular case of sigma-delta modulation for the first time in this work. A Vernier-TDC model based on a sigma-delta modulator is also new in the literature, to our knowledge. There are already reviews of TDC architectures such as [19] and [20]. However, in this review, a single notation is used to derive models based on quantizers and sigma-delta modulators for the main TDC architectures from their respective timing diagrams. The same notation allows a simple comparison between different architectures in terms of time resolution.

In Chap. 4, we focus on the noise performance of the main architectures of ADPLLs. We derive analytical predictions of the phase noise in TDC-based and accumulator-basedADPLLs with noise-shaping TDCs and a DCO driven by a sigma-delta modulator. In order to derive analytical predictions for the ADPLL phase noise, we first explain how to calculate the phase noise of the DCO when its input is known. Then we derive linear models associated with the building blocks in an ADPLL. We use the linear models of the building blocks of an ADPLL to develop a linear model of the full ADPLL. We derive analytical predictions of the ADPLL phase noise from the linear ADPLL model. Finally, we compare Matlab simulations and analytical predictions for an example TDC-based ADPLL architecture. We also show that our results are in very good agreement with predictions obtained by means of the “PLL Design Assistant” [21] which is an automatic design tool for PLL. By contrast with the “PLL Design Assistant” program, which is compiled and therefore cannot be modified by the user, the Matlab scripts that we present are ready to be edited. Hence, the Matlab scripts in this chapter represent a complementary learning tool that gives direct insight into the design equations.

In Chap. 5, we determine the precision of the systems “Quantizer plus Moving Average Filter” and “Sigma-Delta Modulator plus Moving Average Filter” with dither. We show analytically that the difference between the input and output of a “Sigma-Delta Modulator plus Moving Average Filter” is smaller than that of an equivalent “Quantizer plus Moving Average Filter”. The analytical results derived in this chapter are important in order to understand how to exploit noise shaping in ADPLLs. Notice that we determine the precision of systems comprising sigma-delta modulation and dither followed by moving average filters in terms of the maximum difference between the input and the output and the variance of the output in the time domain. In the literature, it is common to analyse the advantages of sigma-delta modulation and dither in the frequency domain [22]. However, the analysis in the frequency domain is usually based on the assumptions that the quantization error of a sigma-delta modulator is white and independent of the input. This white noise approximation is not valid when the output of a sigma-delta modulator exhibits tones. The approach that is presented in this chapter is an alternative to the standard frequency domain analysis and does not require the white noise approximation.

In Chap. 6, we discuss how to simulate an ADPLL with fully nonlinear behavioral models. We show how to realize an efficient behavioral model of an ADPLL that produces the minimum number of samples during a simulation. The equations that we use to implement the efficient model of an ADPLL are related to a sigma-delta modulator. We report example C- and Matlab code that can be used to implement an efficient Simulink model of an ADPLL. We also illustrate how to realize a Simulink S-function that controls the simulation loop while the simulation is running. The modelling approach for ADPLLs that is detailed in this chapter is similar to that described by Staszewski et al. [23]. The technique reported in [23] describes how to realize event-driven models in Verilog-AMS. Models that are event-driven can be built in Verilog and Verilog-AMS by means of the command “timer”. In this chapter, we show how to realize event-driven models in Simulink. The Simulink models that we describe are simple and can be used as learning tools to understand how to deal with the problems that are associated with modeling ADPLLs.

In Chap. 7, we show how to model and calculate the phase noise of an oscillator in Matlab. The approach presented has been adopted in Chap. 4 to calculate the phase noise of an ADPLL. The material included in this chapter refers mostly to Kundert’s work on model oscillators and signals with phase noise in Verilog-AMS [24]. However, we focus more on the steps that are necessary to model a noisy signal and to extract its phase noise. The steps of an example noise extraction procedure are clearly illustrated with Matlab scripts.