Abstract
Multi-Processor System on Chip (MPSoC) offers a set of processors, embedded in one single chip. A parallel application can, then, be scheduled to each processor, in order to accelerate its execution. One problem in MPSoCs is the communication between processors, necessary to run the application. The shared memory provides the means to exchange data. In order to allow for non-blocking parallelism, we based the interconnection network in the crossbar topology. In this kind of interconnection, processors have full access to their own memory module simultaneously. On the other hand, processors can address the whole memory. One processor accesses the memory module of another processor only when it needs to retrieve data generated by the latter. This chapter presents the specification and modeling of an interconnection network based on crossbar topology. The aim of this work is to investigate the performance characteristics of a parallel application running on this platform.
This chapter was developed in collaboration with Fábio Gonçalves Pessanha
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Nedjah, N., de Macedo Mourelle, L. (2014). Particle Swarm Optimization on Crossbar Based MPSoC. In: Hardware for Soft Computing and Soft Computing for Hardware. Studies in Computational Intelligence, vol 529. Springer, Cham. https://doi.org/10.1007/978-3-319-03110-1_4
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DOI: https://doi.org/10.1007/978-3-319-03110-1_4
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-03109-5
Online ISBN: 978-3-319-03110-1
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