Surface Potential Based Analytical Model for Hetero-Dielectric p-n-i-n Double-Gate Tunnel-FET

Part of the Environmental Science and Engineering book series (ESE)

Abstract

In this work a piecewise Surface Potential based analytical model for a Hetero-Dielectric p-n-i-n Double Gate Tunnel FET has been developed which captures the device performance in all regions of operation i.e. Accumulation, Depletion and Inversion Region. Moreover, a comparative study among single High-k dielectric, single Low-k dielectric and Hetero-Dielectric TFET has been done. Here Vgs and Vds dependent explicit equations for surface potential have been derived which are subsequently been made to be channel length dependent. Furthermore, the electrostatic behavior of the device is studied in terms of Lateral Electric Field and Energy Band Diagram. The efficacy of the model has been validated through simulated results obtained using ATLAS device simulation software.

Keywords

Tunnel FET (T-FET) Accumulation Region and Explicit Equation 

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Notes

Acknowledgments

Authors would like to thank Ministry of Science and Technology, Department of Science and Technology, Government of India and University of Delhi. One of the authors Upasana, would like to thank University Grants Commission, Govt. of India for providing necessary financial assistance during the course of this research work.

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Upasana
    • 1
  • Rakhi Narang
    • 1
  • Manoj Saxena
    • 2
  • Mridula Gupta
    • 1
  1. 1.Semiconductor Device Research Laboratory, Department of Electronic ScienceUniversity of DelhiNew DelhiIndia
  2. 2.Department of Electronics, Deen Dayal Upadhayaya CollegeUniversity of DelhiKarampuraIndia

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