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Improved Underlap FinFET with Asymmetric Spacer Permittivities

  • Conference paper
Physics of Semiconductor Devices

Part of the book series: Environmental Science and Engineering ((ENVENG))

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Abstract

A much higher performance can be achieved by the use of a high-K spacer for only the SE region of the Underlap FinFET. We explain this effect using a 3-transistor equivalent circuit in the FinFET device. Our new device design does not increase OFF state current.

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References

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Author information

Authors and Affiliations

  1. Cisco Systems, Bangalore, India

    Saurabh K. Nema

  2. Department of Electronics and Communication Engineering, IIT, Roorkee, India

    M. SaiKiran, P. Singh, Archana Pandey, S. K. Manhas, A. K. Saxena & Anand Bulusu

Authors
  1. Saurabh K. Nema
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  2. M. SaiKiran
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  3. P. Singh
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  4. Archana Pandey
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  5. S. K. Manhas
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  6. A. K. Saxena
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  7. Anand Bulusu
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Corresponding author

Correspondence to Saurabh K. Nema .

Editor information

Editors and Affiliations

  1. Amity Institute for Advanced Research and Studies (Meterials & Devices), Amity University, Noida, Uttar Pradesh, India

    V. K. Jain

  2. Amity Institute for Advanced Research and Studies (Meterials & Devices), Amity University, Noida, Uttar Pradesh, India

    Abhishek Verma

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© 2014 Springer International Publishing Switzerland

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Nema, S.K. et al. (2014). Improved Underlap FinFET with Asymmetric Spacer Permittivities. In: Jain, V., Verma, A. (eds) Physics of Semiconductor Devices. Environmental Science and Engineering(). Springer, Cham. https://doi.org/10.1007/978-3-319-03002-9_67

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