Gate Leakage Current Modeling in Ferroelectric FET
A gate leakage current model is proposed for a negative capacitance or ferroelectric Field Effect Transistor (Fe-FET). A simple gate structure containing a ferroelectric, Lead Zirconate Titanate (PZT) mounted on silicon substrate without any buffer layer between the two is considered. This model is based on Schottky and Poole–Frenkel current conduction mechanisms. It has been found that Poole–Frenkel current conduction mechanism takes place in ferroelectrics and the gate leakage currents in the gate stack containing ferroelectric as dielectric can be modeled using a unified Schottky Poole–Frenkel model.
KeywordsGate leakage Fe-FET Negative capacitance PZT Ferroelectrics
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