Advertisement

T-CAD Design Simulation and Comparative Performance Analysis of 6-T SRAM Cell with Nanoscale SOI and MOS Technology

  • P. Deepika
  • E. Subhasri
  • Sanjoy Deb
Part of the Environmental Science and Engineering book series (ESE)

Abstract

During last few decades, either memory or processor, VLSI circuit efficiency, has been significantly improved through a combination of device scaling, new device structures and material property improvement. In nano-meter region, conventional silicon technology has been suffered from the fundamental physical limitations so some alternative device technologies like Silicon-on-Insulator (SOI) technology has been emerged. Experimentally or theoretically, SOI technology has shown better short channel effect immunity and thus transistor scalability and circuit performance has been improved. In last decade, intense interests have been paid in practical fabrication and compact modelling of SOI MOSFET but little attention has been paid to understand the SOI based circuit performance analysis and improvement. In the present analysis, using TCAD Simulator, six transistors SRAM cell has been designed with SOI and conventional MOSFET nano-structures. SRAM effective reading and writing operations have been compared to implicate the improvement in efficiency with SOI technology. Time delay and power dissipation for both SOI SRAM and MOS SRAM cell has been compared also. It has been observed that nano-SOI SRAM cell shows better reading sensitivity as well as better power efficiency but with little higher delay effect compared to nano-MOS SRAM cell.

SRAM SOI MOSFET Compact model  SPICE Leakage current Time delay 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    F. Gamiz,, A 20 nm low-power triple-gate multibody 1T-SRAM cell, International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), 23-25 April 2012, TaiwanGoogle Scholar
  2. 2.
    Changhwan Shin (PhD Thesis), Advanced MOSFET Designs and Implications for SRAM Scaling, University of California, Berkeley, 2011.Google Scholar
  3. 3.
    Sanjoy Deb, N.Basanta Singh, Nurul Islam, and S.K.Sarkar, Work Function Engineering with Linearly Graded Binary Metal Alloy Gate Electrode for Short Channel SOI MOSFET”, IEEE Transactions on Nano Technology, Volume: 11, Issue: 3, Page(s): 472 – 478, 2012.CrossRefGoogle Scholar
  4. 4.
    Sanjoy Deb, C. J. K Singh, N B Singh, P C Pradhan & S K Sarkar, Design and Performance Comparison of SOI and Conventional MOSFET Based CMOS Inverter, ISDMISC-2011, Proceedings published by International Journal of Computer Applications.Google Scholar
  5. 5.

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.Department of ECEBITSathyamangalamIndia

Personalised recommendations