An OFDMA PHY System on Chip Design Methodology

  • Trio Adiono
Conference paper
Part of the Environmental Science and Engineering book series (ESE)


This topic presents the design methodology for designing a real-time OFDMA based wireless physical layer (PHY) system. An OFDMA based wireless system consists of complex and computationally intensive processing modules, such as FFT/IFFT, User Allocator, Turbo Encoder/Decoder, Channel Estimator and Compensator, MIMO and Time-Frequency Synchronizer. However, the computation has to be done within a very short time regarding to fix frame duration restriction of OFDMA system. On the other hand, the power consumption and chip size also have to be very small due to battery operated system and mobile application. Therefore, optimization has to be done from all stages of design steps, such as from algorithm and architecture exploration, up to implementation level such as design synthesis, and placement and routing. Algorithm and architecture level plays an important role in determining final system performances. Some architecture design method for performance improvement, such as parallel processing, pipelined, folding, unfolding are also used in this design approach. The real-time performance is measured in FPGA based system prototyping. System validation is done in RTL level, Radio Conformance Test and Field Test.




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  1. 1.
    ETSI TS 136 300 v10.2.0 (2011-01). Evolved Universal Terrestrial Radio Access (E-UTRA) and Evolved Universal Terrestrial Radio Access Network (E-UTRAN); Overall description; Stage 2 (3GPP TS 36.300 version 10.2.0 Release 10).Google Scholar
  2. 2.
    3GPP Technical Specification 36.300, ‘Evolved Universal Terrestrial Radio Access (E-UTRA) and Evolved Universal Terrestrial Radio Access Network (E-UTRAN); Overall description; Stage 2 (Release 8)’.Google Scholar
  3. 3.
    T. M. Schmidl and D. C. Cox, “Robust frequency and timing synchronization for OFDM,” IEEE Trans. Commun., vol. 45, no. 12, pp. 1613–1621, Dec. 1997.CrossRefGoogle Scholar
  4. 4.
    J. J. van de Beek, M. Sandell, and P. O. Borjesson, “ML estimation of time and frequency offset in OFDM systems,” IEEE Trans. Signal Processing, vol. 45, no. 7, pp. 1800–1805, July 1997.CrossRefGoogle Scholar
  5. 5.
    W. Eberle, “Wireless Transceiver Systems Design”, Springer, 2008.CrossRefGoogle Scholar
  6. 6.
    T.-D. Chiueh, and P.-Y Tsai, “OFDM Baseband Receiver Design for Wireless Communications”, Singapore: John Wiley and Sons, 2007.Google Scholar
  7. 7.
    W.-H Tseng, et al. “Digital VLSI OFDM Transceiver Architecture for Wireless SoC Design”, IEEE International Symposium on Circuits and Systems (ISCAS), 2005.Google Scholar
  8. 8.
    A. Nilsson, “Design Methodology for memory-efficient multi-standard baseband processors”, Asia-Pacific Conference on Comunications, 2005.Google Scholar
  9. 9.
    K. Masselos, S. Blionas, dan T. Rautio, “Reconfigurability requirements of Wireless communication systems”, IEEE Workshop on Heterogeneous Reconfigurable Systems on Chip, April 2002.Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.Institute Teknologi BandungBandungIndonesia

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