Electrical Characterization of n-ZnO Nanowires/p-Si Based Heterojunction Diodes

Abstract

We report electrical characteristics of n-ZnO NWs/p-Si based heterojunctions diode fabricated by oxidation of thermally deposited metallic Zn on Al:ZnO coated p-Si substrates. The surface morphology of ZnO NWs has been investigated by atomic force microscopy (AFM). The carrier donor concentration of the ZnO NW films and barrier height of the heterojunction diode estimated from the C–V characteristics are 1.54 × 10¹⁵ cm⁻³ and 0.75 eV respectively. The estimated values of the barrier height and ideality factor from room temperature I–V characteristic are 0.73 eV and 2.13 respectively. As obtained value of barrier height from C–V characteristic is a bit higher then I–V characteristic, indicates presence of barrier inhomogeneity at the n-ZnONWs/p-Si interfaces. Furthermore, the value of series resistance $\left( {{\text{R}}_{\text{s}} } \right)$ has also been determined from forward bias I–V characteristics using Chueng’s function