Abstract
Cellular Nonlinear/Nanoscale Networks (CNNs) that can provide parallel processing in massive scale are known to be suitable for neuromorphic applications such as vision systems. In CNNs, synaptic weights can be calculated by digital or analog multiplications. Though conventional CMOS digital circuits can be used in calculating these multiplications for CNN applications, they occupy very large area and consume a large amount of power, especially when multiplications should be calculated in parallel in massive scale. On the other hand, analog circuits seem to be very attractive for calculating multiplications for CNN applications. One possible approach is to multiply the input current by the programmable resistance of a memristor before applying the resulting voltage to a differential pair for the final voltage-to-current conversion. In this chapter we introduce some analog circuits for CNN applications that use the resistance of a memristor in calculating multiplications. In addition we discuss memristor models and some practical problems in CNN circuits that should be resolved using analog memristor-based implementations.
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Notes
- 1.
In the following memristive systems are referred to as memristor systems, whereas the term ideal memristor is used for systems described by (1).
- 2.
For the sake of brevity the explicit time dependency is dropped where it is not strictly necessary.
- 3.
Note that by defining a time evolution rule for the threshold voltages, it was recently demonstrated [23] that an adaptable threshold voltage-based version of the memristor model from [6] may explain the Suppression Principle [24] of the Spike-Timing-Dependent-Plasticity (STDP) Rule [6], which may occur in the case of triplet spikes.
- 4.
Throughout the paper, unless stated otherwise and without loss of generality, we assume that the doped layer is spatially located to the left of the un-doped layer along the horizontal extension of the nano-film [20], and in this case we assign a value of +1 to the memristor polarity coefficient η (see Eq. (6)).
- 5.
Nonlinear memristors models, including the GBCM model, will be considered in the forthcoming publications.
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Acknowledgements
This work was partially supported by the CRT Foundation, under the project no. 2012.1121 and by the Ministry of Foreign Affairs ”Con il contributo del Ministero degli Affari Esteri, Direzione Generale per la Promozione del Sistema Paese”.
The CAD tools were supported by the IC Design Education Center (IDEC), Korea. This work was financially supported by NRF-2013K1A3A1A25038533 through the National Research Foundation of Korea(NRF) funded by the Ministry of Science, ICT & Future Planning.
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Corinto, F., Ascoli, A., Kim, YS., Min, KS. (2014). Cellular Nonlinear Networks with Memristor Synapses. In: Adamatzky, A., Chua, L. (eds) Memristor Networks. Springer, Cham. https://doi.org/10.1007/978-3-319-02630-5_13
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