Abstract
In high-speed transceiver design, most of the issues are caused by the lossy channel which has a low-pass filter characteristic. As shown in Fig. 4.1, to compensate for the channel loss, pre-emphasis at the transmitter is performed and equalization at the receiver is performed. Also, the multi-channel interface causes crosstalk and skew effect. These effects should be covered in DRAM interface design. Other issues in transceiver design are impedance matching, low power design, and error reduction. And, as many techniques are applied in the transceiver, training sequence is needed to set the proper operating point of each technique. Several issues and their solutions will be explained in this chapter.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Reference
K.-h. Kim et al., “A 20-Gb/s 256-Mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter,” IEEE J. Solid-State Circuits, vol.41, no. 1, pp. 127–134, Jan. 2006.
H. Partovi et al., “Single-ended transceiver design techniques for 5.33 Gb/s graphics applications,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 136–137.
Y. Hidaka, “Sign-based-Zero-Forcing Adaptive Equalizer Control,” in CMOS Emerging Technologies Workshop, May 2010.
S.-J. Bae et al., “A 60 nm 6 Gb/s/pin GDDR5 graphics DRAM with multifaceted clocking and ISI/SSN-reduction techniques,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 278–279.
K. Kaviani et al., “A 6.4 Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2013, pp. 306–307.
K.-I. Oh et al., “A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2222–2232, Aug. 2009.
S.-J. Bae et al., “A 40 nm 2 Gb 7 Gb/s/pin GDDR5 SDRAM with a Programmable DQ Ordering Crosstalk Equalizer and Adjustable clock-Tracing BW,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 498–500.
S. H. Wang et al., “A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 648–657, Apr. 2001.
K. Sohn et al., “A 1.2V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 38–40.
C. Park et al., “A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 831–838, Apr. 2006.
D. Lee et al., “Multi-slew-rate output driver and optimized impedance-calibration circuit for 66 nm 3.0 Gb/s/pin DRAM interface,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 280–613.
S. Kim et al., “A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM,” IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 726–734, Jun. 2002.
J. Koo et al., Young Jung Choi, and Chulwoo Kim, “Small-Area High-Accuracy ODT/OCD by calibration of Global On-Chip for 512M GDDR5 application,” in IEEE CICC, Sep. 2009, pp. 717–720.
S.-M. Lee et al., “A 27 % reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance 4xZ0 at TX and RX,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2013, pp. 308–309.
S.-S. Yoon et al., “A fast GDDR5 read CRC calculation circuit with read DBI operation,” in IEEE Asian Solid-State Circuits Conf., Mar. 2008, pp. 249–252.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2014 The Author(s)
About this chapter
Cite this chapter
Kim, C., Song, J., Lee, HW. (2014). Transceiver Design. In: High-Bandwidth Memory Interface. SpringerBriefs in Electrical and Computer Engineering. Springer, Cham. https://doi.org/10.1007/978-3-319-02381-6_4
Download citation
DOI: https://doi.org/10.1007/978-3-319-02381-6_4
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-02380-9
Online ISBN: 978-3-319-02381-6
eBook Packages: EngineeringEngineering (R0)