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High-Bandwidth Memory Interface pp 25–49Cite as

Clock Generation and Distribution

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Abstract

DLL is a popular clock generator in DRAM and duty cycle corrector is an essential block for DDR DRAM. Low skew, low power clock distribution method has become an important issue in high-bandwidth memories.

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Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Korea University, Seongbuk-gu, Seoul, Korea

    Chulwoo Kim & Junyoung Song

  2. SK-Hynix, Icheon-si, Korea

    Hyun-Woo Lee

Authors
  1. Chulwoo Kim
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  2. Junyoung Song
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  3. Hyun-Woo Lee
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Correspondence to Chulwoo Kim .

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Kim, C., Song, J., Lee, HW. (2014). Clock Generation and Distribution. In: High-Bandwidth Memory Interface. SpringerBriefs in Electrical and Computer Engineering. Springer, Cham. https://doi.org/10.1007/978-3-319-02381-6_3

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  • DOI: https://doi.org/10.1007/978-3-319-02381-6_3

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  • Online ISBN: 978-3-319-02381-6

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