Conclusions

Abstract

This book has covered a wide array of topics relating to the design-for-test and test optimization for 3D SICs. These topics were chosen to explore test in many scenarios, including memory-on-memory, memory-on-logic, and logic-on-logic stacks. BIST and probing techniques were explored for pre-bond TSV and scan test. Methods for yield assurance, including BISR architectures and wafer matching, were explained in detail. Optimizations for reducing test cost were also covered, including flows to reduce the delay overhead of DfT architectures and to optimize TAM architectures and test schedules to reduce test time. Together, the topics covered by this book offer an extensive and in-depth look at the cutting-edge of 3D test for students, teachers, researchers, and industry practitioners.