Abstract
The semiconductor industry has relentlessly pursued smaller device sizes and low-power chips in a broad range of market segments, ranging from servers to mobile devices. As transistors continue their miniaturization march through smaller technology nodes, the limits of device scaling tend to be reached. Interconnects, particularly global interconnects, are becoming a bottleneck in integrated circuit (IC) design. Since interconnects do not scale as well as transistors, long interconnects are beginning to dominate circuit delay and power consumption.
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Noia, B., Chakrabarty, K. (2014). Introduction. In: Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs. Springer, Cham. https://doi.org/10.1007/978-3-319-02378-6_1
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DOI: https://doi.org/10.1007/978-3-319-02378-6_1
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