Skip to main content

Abstract

In this chapter a state-of-the-art review on analog integrated circuit (IC) design automation tools applied to the specification translation problem is presented. Having the right topology for a given set of specifications is indispensable for a high performance design. An inadequate topology makes the design more difficult (or even impossible), and may require unnecessary resources, which is not acceptable in high performance designs. Once the topology is selected, the specifications for the overall block are translated to the specifications for the sub-blocks. The specifications are, in this way, passed through the hierarchy. At the lowest level, the translation reduces to circuit sizing, whereas at the higher levels it produce the sub-blocks performance parameters. In the last years, the scientific community proposed many techniques for the automation of the translation task; some apply only at circuit-level or only at system level, while others apply to both. In this study, several circuit-level sizing techniques are sketched and compared, and then, different model-based optimization approaches are outlined.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. M.F.M. Barros, J.M.C. Guilherme, N.C.G. Horta, Analog circuits and systems optimization based on evolutionary computation techniques (Springer, Berlin, 2010)

    Book  MATH  Google Scholar 

  2. M.G.R. Degrauwe, O. Nys, E. Dijkstra et al., IDAC: an interactive design tool for analog CMOS circuits. IEEE J. Solid-State Circuits 22(6), 1106–1116 (1987)

    Article  Google Scholar 

  3. R. Harjani, R.A. Rutenbar, L.R. Carley, OASYS: a framework for analog circuit synthesis. IEEE Trans. Comput.Aided Des. Integr. Circuits Syst. 8(12), 1247–1266 (1989)

    Article  Google Scholar 

  4. N.C. Horta, J.E. Franca, High-level data conversion synthesis by symbolic methods, in Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 4 (1996), pp. 802–805

    Google Scholar 

  5. N. Horta, Analogue and mixed-signal systems topologies exploration using symbolic methods. Analog Integr. Circ. Sig. Process 31(2), 161–176 (2002)

    Article  Google Scholar 

  6. N.C. Horta, J.E. Franca, Algorithm-driven synthesis of data conversion architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10), 1116–1135 (1997)

    Article  Google Scholar 

  7. F. El-Turky, E.E. Perry, BLADES: an artificial intelligence approach to analog circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(6), 680–692 (1989)

    Article  Google Scholar 

  8. B.J. Sheu, J.C. Lee, A.H. Fung, Flexible architecture approach to knowledge-based analogue IC design. IEEE Proc. G Circuits Devices Syst. 137(4), 266–274 (1990)

    Article  Google Scholar 

  9. C.A. Makris, C. Toumazou, Analog IC design automation. II. Automated circuit correction by qualitative reasoning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2), 239–254 (1995)

    Article  Google Scholar 

  10. C. Toumazou, C.A. Makris, Analog IC design automation. I. Automated circuit generation: new concepts and methods. IEEE Trans. Comput.Aided Des. Integr.Circuits Syst. 14(2), 218–238 (1995)

    Article  Google Scholar 

  11. H.Y. Koh, C.H. Sequin, P.R. Gray, OPASYN: a compiler for CMOS operational amplifiers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2), 113–125 (1990)

    Article  Google Scholar 

  12. J.P. Harvey, M.I. Elmasry, B. Leung, STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(11), 1402–1417 (1992)

    Article  Google Scholar 

  13. G.G.E. Gielen, H.C.C. Walscharts, W.M.C. Sansen, Analog circuit design optimization based on symbolic simulation and simulated annealing. IEEE J. Solid-State Circuits 25(3), 707–713 (1990)

    Article  Google Scholar 

  14. G.G.E. Gielen, H.C.C. Walscharts, W.M.C. Sansen, ISAAC: a symbolic simulator for analog integrated circuits. IEEE J. Solid-State Circuits 24(6), 1587–1597 (1989)

    Article  Google Scholar 

  15. K. Swings, W. Sansen, DONALD: a workbench for interactive design space exploration and sizing of analog circuits, in Proceedings of the European Conference on Design Automation, (1991), pp. 475–479

    Google Scholar 

  16. P.C. Maulik, L.R. Carley, D.J. Allstot, Sizing of cell-level analog circuits using constrained optimization techniques. IEEE J. Solid-State Circuits 28(3), 233–241 (1993)

    Article  Google Scholar 

  17. E.S. Ochotta, R.A. Rutenbar, L.R. Carley, Synthesis of high-performance analog circuits in ASTRX/OBLX. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(3), 273–294 (1996)

    Article  Google Scholar 

  18. W. Kruiskamp, D. Leenaerts, DARWIN: CMOS opamp synthesis by means of a genetic algorithm, in Proceedings of the Design Automation Conference, (1995), pp. 433–438

    Google Scholar 

  19. M. del Mar Hershenson, S.P. Boyd, T.H. Lee, GPCAD: a tool for CMOS op-amp synthesis, in InternationBaal Conference on Computer-Aided Design, Digest of Technical Papers of the IEEE/ACM, (1998), pp. 296–303

    Google Scholar 

  20. G. Gielen, P. Wambacq, W.M. Sansen, Symbolic analysis methods and applications for analog circuits: a tutorial overview. Proc. IEEE 82(2), 680–692 (1994)

    Google Scholar 

  21. M. Kuo-Hsuan, P. Po-Cheng, C. Hung-Ming, Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping, in Symposium on Quality Electronic Design (ISQED), (2011), pp. 1–8

    Google Scholar 

  22. A. Torralba, J. Chavez, L.G. Franquelo, FASY: a fuzzy-logic based tool for analog synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7), 705–715 (1996)

    Article  Google Scholar 

  23. A.J. Torralba, J. Chavez, L.G. Franquelo, Fuzzy-logic-based analog design tools. IEEE Micro 16(4), 60–68 (1996)

    Article  Google Scholar 

  24. F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez et al., A vertically integrated tool for automated design of Sigma&Delta modulators. IEEE J. Solid-State Circuits 30(7), 762–772 (1995)

    Article  Google Scholar 

  25. A. Doboli, N. Dhanwada, A. Nunez-Aldana et al., A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. ACM Trans. Des. Autom. Electron. Syst. 9(2), 238–271 (2004)

    Article  Google Scholar 

  26. K. Matsukawa, T. Morie, Y. Tokunaga et al., Design methods for pipeline delta-sigma A-to-D converters with convex optimization, in Design Automation Conference, (2009), pp. 690–695

    Google Scholar 

  27. L.W. Nagel, SPICE2: A Computer Program to Simulate Semiconductor Circuits (EECS Department, University of California, Berkeley, 1975)

    Google Scholar 

  28. W. Nye, D.C. Riley, A. Sangiovanni-Vincentelli et al., DELIGHT.SPICE: an optimization-based system for the design of integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4), 501–519 (1988)

    Article  Google Scholar 

  29. L. Cheng-Wu, S. Pin-Dai, S. Ya-Ting et al., A bias-driven approach for automated design of operational amplifiers., in International Symposium on VLSI Design, Automation and Test, (2009), pp. 118–121

    Google Scholar 

  30. F. Medeiro, F.V. Fernandez, R. Dominguez-Castro et al., A Statistical Optimization-based Approach For Automated Sizing Of Analog Cells., in Conference on Computer-Aided Design, (1994), pp. 594–597

    Google Scholar 

  31. M. Krasnicki, R. Phelps, R.A. Rutenbar et al., MAELSTROM: efficient simulation-based synthesis for custom analog cells, in Design Automation Conference, (1999), pp. 945–950

    Google Scholar 

  32. R. Phelps, M. Krasnicki, R.A. Rutenbar et al., Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(6), 703–717 (2000)

    Article  Google Scholar 

  33. R. Castro-Lopez, O. Guerra, E. Roca, F. Fernandez, An integrated layout-synthesis approach for analog ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7), 1179–1189 (2008)

    Google Scholar 

  34. N. Lourenço, N. Horta, GENOM-POF: Multi-Objective evolutionary synthesis of analog ICs with corners validation, in GECCO’ 12: Proceedings of the Fourteenth International Conference on Genetic and Evolutionary Computation Conference, (2012), pp. 1119–1126

    Google Scholar 

  35. T. Massier, H. Graeb, U. Schlichtmann, The sizing rules method for CMOS and bipolar analog integrated circuit synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12), 2209–2222 (2008)

    Google Scholar 

  36. G. Alpaydin, S. Balkir, G. Dundar, An evolutionary approach to automatic synthesis of high-performance analog integrated circuits. IEEE Trans. Evol. Comput. 7(3), 240–252 (2003)

    Article  Google Scholar 

  37. F. De Bernardinis, M.I. Jordan, A. SangiovanniVincentelli, Support vector machines for analog circuit performance representation, in Design Automation Conference, (2003),pp. 964–969

    Google Scholar 

  38. G.A. Wolfe, Performance Macro-Modeling Techiniques for Fast Analog Circuit Synthesis, University of Cincinnati, 2004

    Google Scholar 

  39. M. Barros, J. Guilherme, N. Horta, GA-SVM optimization kernel applied to analog IC design automation., in IEEE Internation Conference on Electronics, (2006), pp. 486–489

    Google Scholar 

  40. R. Castro-Lopez, E. Roca, F.V. Fernandez, Multimode pareto fronts for design of reconfigurable analogue circuits. Electron. Lett. 45(2), 95–96 (2009)

    Google Scholar 

  41. E. Denize, G. Dundar, Hierarchical performance estimation of analog blocks using pareto fronts. Ph.D., Research in Microelectronics and Electronics, 2010

    Google Scholar 

  42. T. McConaghy, G. Gielen, Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization, in IEEE International Symposium on Circuits and Systems (ISCAS), (2005), pp.1298–1301

    Google Scholar 

  43. T. McConaghy, G. Gielen, Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization, in IEEE International Symposium on Circuits and Systems (ISCAS), (2005), pp. 1298–1301

    Google Scholar 

  44. W. Daems, G. Gielen, W. Sansen, Simulation-based generation of posynomial performance models for sizing of analog integrated circuits. IEEE Trans. CAD 22(5), 517–534 (2003)

    Article  Google Scholar 

  45. T. McConaghy, T. Eecklelaert, G. Gielen, CAFFEINE: Template-free symbolic model generation of analog circuits via canonical form functions and genetic programming, in Design, Automation and Teste in Europe 2, (2005), pp. 1082–1087

    Google Scholar 

  46. N. Ampazis, S.J. Perantonis, OLMAN neural networks toolbox for Matlab (2002), http://iit.demokritos.gr/~abazis/toolbox/

  47. R.E. Schapire, The boosting approach to machine learning: an overview, in MSRI Workshop on Nonlin. Estimation and Classification, (2002)

    Google Scholar 

  48. J.H. Friedman, Multivariate adaptive regression splines. Ann. Stat 19, 1–141 (1991)

    Article  MATH  Google Scholar 

  49. H. Drucker, C.J.C. Burges, L. Kaufman, A. Smola, V. Vapnik, in Adv. in Neural Information Processing Systems 9, ed. by M.C. Mozer, J.I. Jordan, T. Petscbe.Support vector regression machines, (MIT Press, Cambridge, 1997), pp. 155–161

    Google Scholar 

  50. D.R. Jones, M. Schonlau, W.J. Welch, Efficient global optimization of expensive black-box functions. J. Glob. Opt 13(4), 455–492 (1998)

    Article  MathSciNet  MATH  Google Scholar 

  51. D.C. Montgomery, Design and Analysis of Experiments, 5th edn. (John Wiley and Sons, New York, 2001)

    Google Scholar 

  52. Z.Q. Ning, T. Mouthaan, H. Wallinga, SEAS: a simulated evolution approach for analog circuit synthesis, in Proceedings of the IEEE Custom Integrated Circuits Conference, (1991) pp. 5.2.1–5.2.4

    Google Scholar 

  53. H. Chang, A. Sangiovanlli-Vincentelli, F. Balarin et al., A top-down, constraint-driven design methodology for analog integrated circuits, in Proceedings of the IEEE Custom Integrated Circuits, vol. 3–6 (1992), pp. 8.4.1–8.4.6

    Google Scholar 

  54. P.C. Maulik, L.R. Carley, R.A. Rutenbar, A mixed-integer nonlinear programming approach to analog circuit synthesis, in Proceedings of Design Automation Conference, (1992), pp. 698–703

    Google Scholar 

  55. P.C. Maulik, L.R. Carley, R.A. Rutenbar, Integer programming based topology selection of cell-level analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4), 401–412 (1995)

    Article  Google Scholar 

  56. J.R. Koza, F.H. Bennett III, D. Andre et al., Automated synthesis of analog electrical circuits by means of genetic programming. IEEE Trans. Evol. Comput. 1(2), 109–128 (1997)

    Article  Google Scholar 

  57. M. Del Mar Hershenson, S. P. Boyd, T. H. Lee, GPCAD: a tool for CMOS op-amp synthesis, in International Conference on Computer-Aided Design, Digest of Technical Papers of the IEEE/ACM,, vol. 8–12 (1998), pp. 296–303

    Google Scholar 

  58. J.D. Lohn, S.P. Colombano, A circuit representation technique for automated circuit design. IEEE Trans. Evol. Comput. 3(3), 205–219 (1999)

    Article  Google Scholar 

  59. T. Sripramong, C. Toumazou, The invention of CMOS amplifiers using genetic programming and current-flow analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11), 1237–1252 (2002)

    Article  Google Scholar 

  60. C. Shoou-Jinn, H. Hao-Sheng, S. Yan-Kuin, Automated passive filter synthesis using a novel tree representation and genetic programming. IEEE Trans. Evol. Comput. 10(1), 93–100 (2006)

    Article  Google Scholar 

  61. R. Castro-Lopez, O. Guerra, E. Roca et al., An Integrated Layout-Synthesis Approach for Analog ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7), 1179–1189 (2008)

    Article  Google Scholar 

  62. T. McConaghy, P. Palmers, M. Steyaert et al., Trustworthy genetic programming-based synthesis of analog circuit topologies using hierarchical domain-specific building blocks. IEEE Trans. Evol. Comput. 99, 1–14 (2011)

    Google Scholar 

  63. P. Palmers, T. McConnaghy, M. Steyaert et al., Massively Multi-Topology Sizing of Analog Integrated Circuits (Design, Automation and Teste in Europe, 2009), pp. 706–711

    Google Scholar 

  64. A. Pradhan, R. Vemuri, Efficient synthesis of a uniformly spread layout aware pareto surface for analog circuits, in 22nd International Conference on VLSI Design, (2009), pp. 131–136

    Google Scholar 

  65. Y. Hongying, H. Jingsong, Evolutionary design of operational amplifier using variable-length differential evolution algorithm, in International Conference on Computer Application and System Modeling (ICCASM), (2010), pp. V4-610–V4-614

    Google Scholar 

  66. E. Roca, R. Castro-Lopez, F.V. Fernandez, Hierarchical synthesis based on pareto-optimal fronts, in European Conference on Circuit Theory and Design, (2009), pp. 755–758

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Frederico A. E. Rocha .

Rights and permissions

Reprints and permissions

Copyright information

© 2014 The Author(s)

About this chapter

Cite this chapter

Rocha, F.A.E., Martins, R.M.F., Lourenço, N.C.C., Horta, N.C.G. (2014). State-of-the-Art on Automatic Analog IC Sizing. In: Electronic Design Automation of Analog ICs combining Gradient Models with Multi-Objective Evolutionary Algorithms. SpringerBriefs in Applied Sciences and Technology(). Springer, Cham. https://doi.org/10.1007/978-3-319-02189-8_2

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-02189-8_2

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-02188-1

  • Online ISBN: 978-3-319-02189-8

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics