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Investigations on Transport Properties of Poly-silicon Nanowire Transistors Featuring Independent Double-Gated Configuration Under Cryogenic Ambient

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Toward Quantum FinFET

Part of the book series: Lecture Notes in Nanoscale Science and Technology ((LNNST,volume 17))

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Abstract

Transport properties of poly-Si nanowire transistors, which were fabricated by a simple and low-cost method, are examined in this chapter. The proposed device features two independent gates and thus allows more flexible operation. Electrical measurements performed under cryogenic ambient displayed intriguing characteristics in terms of length-dependent abrupt switching behavior for one of the single-gated modes that is in obvious conflict with the conventional theory concerning short channel effects. Through simulation and experimental verification, it was found that such phenomenon is related to a number of structural parameters, and the root cause was identified to be the nonuniformly distributed dopants introduced by ion implantation.

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References

  1. Im, M., Han, J.W., Lee, H., Yu, L.E., Kim, S., Kim, C.H., Jeon, S.C., Kim, K.H., Lee, G.S., Oh, J.S., Park, Y.C., Lee, H.M., Choi, Y.K.: Multiple-gate CMOS thin-film transistor with polysilicon nanowire. IEEE Electron Device Lett. 29, 102–105 (2008)

    Article  ADS  Google Scholar 

  2. Duan, X.: Nanowire thin-film transistors: a new avenue to high-performance macroelectronics. IEEE Trans. Electron Dev. 55, 3056–3062 (2008)

    Article  ADS  Google Scholar 

  3. Hisamoto, D., Lee, W.C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T.J., Bokor, J., Hu, C.: FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Dev. 47, 2320–2325 (2000)

    Article  ADS  Google Scholar 

  4. Lue, H.T., Hsu, T.H., Hsiao, Y.H., Hong, S.P., Wu, M.T., Hsu, F.H., Lien, N.Z., Wang, S.Y., Hsieh, J.Y., Yang, L.W., Yang, T., Chen, K.C., Hsieh, K.Y., Lu, C.Y.: A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device. In: Symposium on VLSI technology. Digest of technical papers, pp. 131–132 (2010)

    Google Scholar 

  5. Hsu, T.H., Lue, H.T., Hsieh, C.C., Lai, E.K., Lu, C.P., Hong, S.P., Wu, M.T., Hsu, F.H., Lien, N.Z., Hsieh, J.Y., Yang, L.W., Yang, T., Chen, K.C., Hsieh, K.Y., Liu, R., Lu, C.Y.: Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application. In: IEDM technical digest, pp. 629–632 (2009)

    Google Scholar 

  6. Suk, S.D., Li, M., Yeoh, Y.Y., Yeo, K.H., Ha, J.K., Lim, H., Park, H.W., Kim, D.W., Chung, T.Y., Oh, K.S., Lee, W.S.: Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure. In: Symposium on VLSI technology. Digest of technical papers, pp. 142–143 (2009)

    Google Scholar 

  7. Hsiao, Y.H., Lue, H.T., Chen, W.C., Chen, C.P., Chang, K.P., Shih, Y.H., Tsui, B.Y., Lu, C.Y.: Modeling the variability caused by random grain boundary and trap-location induced asymmetrical read behavior for a tight-pitch vertical gate 3D NAND Flash memory using double-gate thin-film transistor (TFT) device. In: IEDM technical digest, pp. 609–612 (2012)

    Google Scholar 

  8. Uchikoga, S.: Low-temperature polycrystalline silicon thin-film transistor technologies for system-on-glass displays. MRS Bull. 27, 881–886 (2002)

    Article  Google Scholar 

  9. Saitoh, M., Murakami, T., Hiramoto, T.: Large Coulomb blockade oscillations at room temperature in ultranarrow wire channel MOSFET formed by slight oxidation process. IEEE Trans. Nanotechnol. 2, 241–245 (2003)

    Article  ADS  Google Scholar 

  10. Akhavan, N.D., Afzalian, A., Lee, C.W., Yan, R., Ferain, I., Razavi, P., Fagas, G., Colinge, J.P.: Simulation of quantum current oscillations in trigate SOI MOSFETs. IEEE Trans. Electron Dev. 57, 1102–1109 (2010)

    Article  ADS  Google Scholar 

  11. Buin, A.K., Verma, A., Anantram, M.P.: Carrier-phonon interaction in small cross-sectional silicon nanowires. J. Appl. Phys. 104, 053716-1–053716-9 (2008)

    Article  ADS  Google Scholar 

  12. Chau, R., Datta, S., Doczy, M., Doyle, B., Kavalieros, J., Metz, M.: High-κ/metal-gate stack and its MOSFET characteristics. IEEE Electron Device Lett. 25, 408–410 (2004)

    Article  ADS  Google Scholar 

  13. Wong, H.S.P.: Beyond the conventional transistor. IBM J. Res. Dev. 46, 133–168 (2002)

    Article  Google Scholar 

  14. Doyle, B., Boyanov, B., Datta, S., Doczy, M., Hareland, S., Jin, B., Kavalieros, J., Linton, T., Rios, R., Chau, R.: Tri-gate fully-depleted CMOS transistors: fabrication, design and layout. In: Symposium on VLSI technology. Digest of technical papers, pp. 133–134 (2003)

    Google Scholar 

  15. Yang, F.L., Chen, H.Y., Chen, F.C., Huang, C.C., Chang, C.Y., Chiu, H.K., Lee, C.C., Chen, C.C., Huang, H.T., Chen, C.J., Tao, H.J., Yeo, Y.C., Liang, M.S., Hu, C.: 25 nm CMOS omega FETs. In: IEDM technical digest, pp. 255–258 (2002)

    Google Scholar 

  16. Singh, N., Agarwal, A., Bera, L.K., Liow, T.Y., Yang, R., Rustagi, S.C., Tung, C.H., Kumar, R., Lo, G.Q., Balasubramanian, N., Kwong, D.L.: High-performance fully depleted silicon nanowire (diameter ≦ 5 nm) gate-all-around CMOS devices. IEEE Electron Device Lett. 27, 383–386 (2006)

    Article  ADS  Google Scholar 

  17. Natori, K.: Compact modeling of ballistic nanowire MOSFETs. IEEE Trans. Electron Dev. 55, 2877–2885 (2008)

    Article  ADS  Google Scholar 

  18. Colinge, J.P., Alderman, J.C., Xiong, W., Cleavelin, C.R.: Quantum-mechanical effects in trigate SOI MOSFETs. IEEE Trans. Electron Dev. 53, 1131–1136 (2006)

    Article  ADS  Google Scholar 

  19. Colinge, J.P., Quinn, A.J., Floyd, L., Redmond, G., Alderman, J.C., Xiong, W., Cleavelin, C.R., Schulz, T., Schruefer, K., Knoblinger, G., Patruno, P.: Low-temperature electron mobility in trigate SOI MOSFETs. IEEE Electron Device Lett. 27, 120–122 (2006)

    Article  ADS  Google Scholar 

  20. Thelander, C., Agarwal, P., Brongersma, S., Eymery, J., Feiner, L.F., Forchel, A., Scheffler, M., Riess, W., Ohlsson, B.J., Gosele, U., Samuelson, L.: Nanowire-based one-dimensional electronics. Mater. Today 9, 28–35 (2006)

    Article  Google Scholar 

  21. Majima, H., Ishikuro, H., Hiramoto, T.: Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFETs. IEEE Electron Device Lett. 21, 396–398 (2000)

    Article  ADS  Google Scholar 

  22. Rustagi, S.C., Singh, N., Lim, Y.F., Zhang, G., Wang, S., Lo, G.Q., Balasubramanian, N., Kwong, D.L.: Low-temperature transport characteristics and quantum-confinement effects in gate-all-around Si-nanowire n-MOSFET. IEEE Electron Device Lett. 28, 909–921 (2007)

    Article  ADS  Google Scholar 

  23. Mojica, D.C., Niquet, Y.M.: Stark effect in GaN/AlN nanowire heterostructures: influence of strain relaxation and surface states. Phys. Rev. B 81, 195313-1–195313-10 (2010)

    ADS  Google Scholar 

  24. Jin, S., Fischetti, M.V., Tang, T.W.: Differential conductance fluctuations in silicon nanowire transistors caused by quasiballistic transport and scattering induced intersubband transitions. Appl. Phys. Lett. 92, 082103-1–082103-3 (2009)

    ADS  Google Scholar 

  25. Wang, J., Polizzi, E., Lundstrom, M.: A computational study of ballistic silicon nanowire transistors. In: IEDM technical digest, pp. 695–698 (2003)

    Google Scholar 

  26. Natori, K.: Ballistic metal-oxide-semiconductor field effect transistor. J. Appl. Phys. 76, 4879–4890 (1994)

    Article  ADS  Google Scholar 

  27. Natori, K.: Scaling limit of the MOS transistor—a ballistic MOSFET. IEICE Trans. Electron. E84-C, 1029–1036 (2001)

    Google Scholar 

  28. Barral, V., Poiroux, T., Barraud, S., Andrieu, F., Faynot, O., Munteanu, D., Autran, J.L., Deleonibus, S.: Evidences on the physical origin of the unexpected transport degradation in ultimate n-FDSOI devices. IEEE Trans. Nanotechnol. 8, 167–173 (2009)

    Article  ADS  Google Scholar 

  29. Cros, A., Romanjek, K., Fleury, D., Harrison, S., Cerutti, R., Coronel, P., Dumont, B., Pouydebasque, A., Wacquez, R., Duriez, B., Gwoziecki, R., Boeuf, F., Brut, H., Ghibaudo, G., Skotnicki, T.: Unexpected mobility degradation for very short devices: a new challenge for CMOS scaling. In: IEDM technical digest, pp. 663–666 (2006)

    Google Scholar 

  30. Shur, M.S.: Low ballistic mobility in submicron HEMTs. IEEE Electron Device Lett. 23, 511–513 (2002)

    Article  ADS  Google Scholar 

  31. Wang, R., Liu, H., Huang, R., Zhuge, J., Zhang, L., Kim, D.W., Zhang, X., Park, D., Wang, Y.: Experimental investigations on carrier transport in Si nanowire transistors: ballistic efficiency and apparent mobility. IEEE Trans. Electron Dev. 55 (2008)

    Google Scholar 

  32. Knoch, J., Riess, W., Appenzeller, J.: Outperforming the conventional scaling rules in the quantum-capacitance limit. IEEE Electron Device Lett. 29, 372–374 (2008)

    Article  ADS  Google Scholar 

  33. Appenzeller, J., Knoch, J., Björk, M.T., Riel, H., Schmid, H., Riess, W.: Toward nanowire electronics. IEEE Trans. Electron Dev. 55, 2827–2845 (2008)

    Article  ADS  Google Scholar 

  34. Lin, H.C., Chen, W.C., Lin, C.D., Huang, T.Y.: Performance enhancement in double-gated poly-Si nanowire transistors with reduced nanowire channel thickness. IEEE Electron Device Lett. 30, 644–646 (2009)

    Article  ADS  Google Scholar 

  35. Chen, W.C., Lin, H.C., Chang, Y.C., Lin, C.D., Huang, T.Y.: In situ doped source/drain for performance enhancement of double-gated poly-Si nanowire transistors. IEEE Trans. Electron Dev. 57, 1608–1615 (2010)

    Article  MathSciNet  ADS  Google Scholar 

  36. Chen, W.C., Lin, H.C., Lin, Z.M., Hsu, C.T., Huang, T.Y.: A study on low temperature transport properties of independent double-gated poly-Si nanowire transistors. Nanotechnology 21, 435201-1–435201-7 (2010)

    ADS  Google Scholar 

  37. Falckenberg, R., Doering, E., Oppolzer, H.: Surface roughness and grain growth of thin p-doped polycrystalline Si-films. In: Proceedings of the Electrochemical Society Meeting, p. 1492 (1979)

    Google Scholar 

  38. Seto, J.Y.W.: The electrical properties of polycrystalline silicon films. J. Appl. Phys. 46, 5247–5254 (1975)

    Article  ADS  Google Scholar 

  39. Lin, Z.M., Lin, H.C., Chen, W.C., Huang, T.Y.: Insight into the performance enhancement of double-gated polycrystalline silicon thin-film transistors with ultrathin channel. Appl. Phys. Lett. 96, 072108-1–072108-3 (2010)

    ADS  Google Scholar 

  40. Puigdollers, J., Dosev, D., Orpella, A., Voz, C., Peiro, D., Bertomeu, J., Marsal, L.F., Pallares, J., Andreu, J., Alcubilla, R.: Microcrystalline silicon thin film transistors obtained by hot-wire CVD. Mater. Sci. Eng. B 69–70, 526–529 (2000)

    Article  Google Scholar 

  41. Puigdollers, J., Orpella, A., Dosev, D., Voz, C., Peiro, D., Pallares, J., Marsal, L.F., Bertomeu, J., Andreu, J., Alcubilla, R.: Thin film transistors obtained by hot wire CVD. J. Non Cryst. Solids 266–269(part 2), 1304–1309 (2000)

    Article  Google Scholar 

  42. Sze, S.M., Ng, K.K.: Physics of semiconductor devices, 3rd edn. Wiley-Interscience, Hoboken (2007)

    Google Scholar 

  43. Taur, Y., Ning, T.H.: Fundamentals of modern VLSI devices. Cambridge University Press, Cambridge (1998)

    Google Scholar 

  44. Boeuf, F., Jehl, X., Sanquer, M., Skotnicki, T.: Controlled single-electron effects in nonoverlapped ultra-short silicon field effect transistors. IEEE Trans. Nanotechnol. 2, 144–148 (2003)

    Article  ADS  Google Scholar 

  45. Padilla, A., Yeung, C.W., Shin, C., Hu, C., Liu, T.J.K.: Feedback FET: a novel transistor exhibiting steep switching behavior at low bias voltages. In: IEDM technical digest, pp. 171–174 (2008)

    Google Scholar 

  46. Lin, H.C., Hung, C.H., Chen, W.C., Lin, Z.M., Hsu, H.H., Huang, T.Y.: Origin of hysteresis in current–voltage characteristics of polycrystalline silicon thin-film transistors. J. Appl. Phys. 105, 054502-1–054502-6 (2009)

    ADS  Google Scholar 

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Acknowledgments

The authors would like to thank the staff at National Nano Device Laboratories (NDL) and Nano Facility Center (NFC) of NCTU for assistance in device fabrication, Prof. Pei-Wen Li of National Central University for support of the cryogenic measurement utilities, and Prof. Bing-Yue Tsui of NCTU for assistance in TEM characterization.

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Authors and Affiliations

  1. Emerging Central Laboratory, Macronix International Co., Ltd, Hsinchu, 300, Taiwan, ROC

    Wei-Chen Chen

  2. Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, 300, Taiwan, ROC

    Horng-Chih Lin

  3. National Nano Device Laboratories, Hsinchu, 300, Taiwan, ROC

    Horng-Chih Lin

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  1. Wei-Chen Chen
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Correspondence to Wei-Chen Chen .

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Editors and Affiliations

  1. Engineering Research Center for Semiconductor Integrated Technology, Chinese Academy of Sciences, Beijing, People's Republic of China

    Weihua Han

  2. Engineering Research Center for Semiconductor Integrated Technology, Chinese Academy of Sciences, Beijing, People's Republic of China

    Zhiming M. Wang

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Chen, WC., Lin, HC. (2013). Investigations on Transport Properties of Poly-silicon Nanowire Transistors Featuring Independent Double-Gated Configuration Under Cryogenic Ambient. In: Han, W., Wang, Z. (eds) Toward Quantum FinFET. Lecture Notes in Nanoscale Science and Technology, vol 17. Springer, Cham. https://doi.org/10.1007/978-3-319-02021-1_9

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