Abstract
As the gate length of a metal oxide semiconductor field effect transistor (MOSFET) decreases, vertical channel transistors, such as the fin-typed field effect transistors (FinFETs) have attracted much attention because of their promising characteristics. In this chapter, we explore the electrical characteristics of 16 nm multi-fin FinFETs with different fin aspect ratios [AR = fin height (H fin)/fin width (W fin)]. The 16-nm multi-fin FinFET device and circuits’ characteristics are simulated by solving a set of 3D quantum-mechanically corrected transport equations coupling with circuit nodal equations self-consistently. Device’s electrical characteristics and their fluctuation are discussed with respect to the AR varying from 0.5 to 2 including the number of silicon channel fins. Dynamic and transfer characteristics of static random access memory, inverter, and analog circuits using single-/multiple-fin FinFETs are further discussed, respectively.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
James, D.: Intel Ivy Bridge unveiled – the first commercial tri-gate, high-k, metal-gate CPU. In: IEEE international custom integrated circuits conference, pp. 1–4 (2012)
Damaraju, S., George, V., Jahagirdar, S., Khondker, Milstrey, T.R., Sarkar, S., Siers, S., Stolero, I., Subbiah, A.: A 22nm IA multi-CPU and GPU system-on-chip. In: IEEE international solid-state circuits conference digest of technical papers, pp. 56–57 (2012)
Auth, C.: 22-nm fully-depleted tri-gate CMOS transistors. In: IEEE international custom integrated circuits conference, pp. 1–6 (2012)
Karl, E., Yih, W., Ng, Y.-G., Guo, Z., Hamzaoglu, F., Bhattacharya, U., Zhang, K., Mistry, K., Bohr, M.: A 4.6 GHZ 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. In: IEEE international solid-state circuits conference digest of technical papers, pp. 230–232 (2012)
Kulkarni, J., Geuskens, B., Karnik, T., Khellah, M., Tschanz, J., De, V.: Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. In: IEEE international solid-state circuits conference digest of technical papers, pp 234–236 (2012)
Seifert, N., Gill, B., Jahinuzzaman, S., Basile, J., Ambrose, V., Shi, Q., Allmon, R., Bramnik, A.: Soft error susceptibilities of 22 nm tri-gate devices. IEEE Trans. Nucl. Sci. 59, 2666–2673 (2012)
Auth, C., Allen, C., Blattner, A., Bergstrom, D., Brazier, M., Bost, M., Buehler, M., Chikarmane, V., Ghani, T., Glassman, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., Hentges, P., Heussner, R., Hicks, J., Ingerly, D., Jain, P., Jaloviar, S., James, R., Jones, D., Jopling, J., Joshi, S., Kenyon, C., Liu, H., McFadden, R., McIntyre, B., Neirynck, J., Parker, C., Pipes, L., Post, I., Pradhan, S., Prince, M., Ramey, S., Reynolds, T., Roesler,J., Sandford, J., Seiple, J., Smith, P., Thomas, C., Towner, D., Troeger, T., Weber, C., Yashar, P., Zawadzki, K., Mistry, K.: A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. In: Symposium on VLSI technology. Digest of technical papers, pp. 131–132 (2012)
Kuhn, K.J., Giles, M.D., Becher, D., Kolar, P., Kornfeld, A., Kotlyar, R., Ma, S., Maheshwari, T.A., Mudanai, S.: Process technology variation. IEEE Trans. Electron Dev. 58, 2197–2208 (2011)
Li, Y., Hwang, C.-H., Li, T.-Y.: Random-dopant-induced variability in nano-CMOS devices and digital circuits. IEEE Trans. Electron Dev. 56, 1588–1597 (2009)
Li, Y., Hwang, C.-H., Li, T.-Y., Han, M.-H.: Process-variation effect, metal-gate work-function fluctuation, and random-dopant fluctuation in emerging CMOS technologies. IEEE Trans. Electron Dev. 57, 437–447 (2010)
Baravelli, E., Jurczak, M., Speciale, N., De Meyer, K., Dixit, A.: Impact of LER and random dopant fluctuations on FinFET matching performance. IEEE Trans. Nanotechnol. 7, 291–298 (2008)
Weber, O., Faynot, O., Andrieu, F., Buj-Dufournet, C., Allain, F., Scheiblin, P., Foucher, J., Daval, N., Lafond, D., Tosti, L., Brevard, L., Rozeau, O., Fenouillet-Beranger, C., Marin, M., Boeuf, F., Delprat, D., Bourdelle, K., Nguyen B.Y., Deleonibus, S.: High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding. In: International electron device meeting. Technical digest, pp. 245–248 (2008)
Li, Y., Hwang, C.-H., Han, M.-H.: Simulation of characteristic variation in 16 nm gate FinFET devices due to intrinsic parameter fluctuations. Nanotechnology 21, 095203 (2010)
Li, Y., Hwang, C.-H., Li, T.-Y.: Discrete-dopant-induced timing fluctuation and suppression in nanoscale CMOS circuit. IEEE Trans. Circ. Syst. II Express Briefs 56, 379–383 (2009)
Ancona, M.G., Tiersten, H.F.: Macroscopic physics of the silicon inversion layer. Phys. Rev. B 35, 7959–7965 (1987)
Odanaka, S.: Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures. IEEE Trans. Comput. Aided Des. Integr. Circ. Sys. 23, 837–842 (2004)
Tang, T.-W., Wang, X., Li, Y.: Discretization scheme for the density-gradient equation and effect of boundary conditions. J. Comput. Electron. 1, 389–393 (2002)
Li, Y., Sze, S.M., Chao, T.S.: A practical implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulation. Eng. Comput. 18, 124–137 (2002)
Cheng, B., Roy, S., Asenov, A.: Impact of intrinsic parameter fluctuations on SRAM cell design. In: Proceedings of international solid-state and integrated circuit technology conference, pp. 1290–1292 (2006)
Cheng, B., Roy, S., Asenov, A.: The scalability of 8T-SRAM cells under the influence of intrinsic parameter fluctuations. In: Proceedings of European solid-state circuits conference, pp. 93–96 (2007)
Cheng, B., Roy, S., Asenov, A.: CMOS 6T SRAM cell design subject to “atomistic” fluctuations. Solid State Electron. 51, 565–571 (2007)
Bhavnagarwala, A.J., Tang, X., Meindl, J.D.: The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. Solid State Circ. 36, 658–665 (2001)
Hill, C.: Definitions of noise margin in logic systems. Mullard Tech. Commun. 89, 239–245 (1967)
Li, Y., Liu, J.-L., Chao, T.-S., Sze, S.M.: A new parallel adaptive finite volume method for the numerical simulation of semiconductor devices. Comput. Phys. Commun. 142, 285–289 (2001)
Kim, S.M., Yoon, E.J., Jo, H.J., Li, M., Oh, C.W., Lee, S.Y., Yeo, K.H., Kim, M.S., Kim, S.H., Choe, D.U., Choe, J.D., Suk, S.D., Kim, D., Park, D., Kim, K., Ryu, B.: A novel multi-channel field effect transistor (McFET) on bulk Si for high performance Sub-80 nm application. In: International electron device meeting. Technical digest, pp. 639–642 (2004)
Bohr, M.: The evolution of scaling from the homogeneous era to the heterogeneous era. In: International electron device meeting. Technical digest, pp. 1–6 (2011)
Li, Y., Hwang, C.-H.: Discrete-dopant-induced characteristic fluctuations in 16 nm multiple-gate silicon-on-insulator devices. J. Appl. Phys. 102, 084509 (2007)
Li, Y., Hwang, C.-H.: Effect of fin angle on electrical characteristics of nanoscale round-top-gate bulk FinFETs. IEEE Trans. Electron Dev. 54, 3426–3429 (2007)
Li, Y., Yu, S.-M., Lee, J.-W.: Quantum mechanical corrected simulation program with integrated circuit emphasis model for simulation of ultrathin oxide metal-oxide-semiconductor field effect transistor gate tunneling current. Jpn. J. Appl. Phys. 44, 2132–2136 (2005)
Li, Y., Hwang, C.-H.: High-frequency characteristic fluctuations of nano-MOSFET circuit induced by random dopants. IEEE Trans. Microw. Theor. Tech. 56, 2726–2733 (2008)
Grasser, T., Selberherr, S.: Mixed-mode device simulation. Microelectron. J. 31, 873–881 (2000)
Li, Y., Yu, S.-M.: A parallel adaptive finite volume method for nanoscale double-gate MOSFETs simulation. J. Comput. Appl. Math. 175, 87–99 (2005)
Seevinck, E., List, F.J., Lohstroh, J.: Static-noise margin analysis of MOS SRAM cells. IEEE J. Solid State Circ. 22, 748–754 (1987)
Frank, D.J., Laux, S.E., Fischetti, M.V.: Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go. In: International electron device meeting. Technical digest, pp. 553–556 (1992)
Yang, F.L., Lee, D.H., Chen, H.Y., Chang, C.Y., Liu, S.D., Huang, C.C., Chung, T.X., Chen, H.W., Huang, C.C., Liu, Y.H., Wu, C.C., Chen, C.C., Chen, S.C., Chen, Y.T., Chen, Y.H., Chen, C.J., Chan, B.W., Hsu, P.F., Shieh, J.H., Tao, H.J., Yeo, Y.C., Li, Y., Lee, J., Chen, W.P., Liang, M.S., Hu, C.: 5nm-gate nanowire FinFET. In: Symposium on VLSI technology. Digest of technical papers, pp. 196–197 (2004)
Li, Y., Chou, H.-M., Lee, J.-W.: Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire Fin-FETs. IEEE Trans. Nanotechnol. 4, 510–516 (2005)
Li, Y., Yu, S.-M., Hwang, J.-R., Yang, F.-L.: Discrete dopant fluctuated 20nm/15nm-gate planar CMOS. IEEE Trans. Electron Dev. 55, 1449–1455 (2008)
International Technology Roadmap for Semiconductors (ITRS) 2007 Edition
Li, Y., Hwang, C.-H., Huang, H.-M.: Large-scale atomistic approach to discrete-dopant-induced characteristic fluctuations in silicon nanowire transistors. Phys. Status Solidi A Appl. Mater. Sci. 205, 1505–1510 (2008)
Li, Y., Yu, S.-M.: Comparison of random-dopant-induced threshold voltage fluctuation in nanoscale single-, double-, and surrounding-gate field-effect transistors. Jpn. J. Appl. Phys. 45, 6860–6865 (2006)
Li, Y., Hwang, C.-H., Cheng, H.-W.: Discrete-dopant-fluctuated transient behavior and variability suppression in 16-nm-gate complementary metal-oxide-semiconductor field-effect transistors. Jpn. J. Appl. Phys. 48, 04C051 (2009)
Li, Y., Hwang, C.-H.: Discrete-dopant-fluctuated threshold voltage roll-off in sub-16nm bulk FinFETs. Jpn. J. Appl. Phys. 47, 2580–2584 (2008)
Endo, K., Ishikawa, Y., Liu, Y., Masahara, M., Matsukawa, T., O’uchi, S., Ishii, K., Yamauchi, H., Tsukada, J., Suzuki, E.: Experimental evaluation of effects of channel doping on characteristics of FinFETs. Electron Dev. Lett. 28, 1123–1125 (2007)
Matsukawa, T., Endo, K., Ishikawa, Y., Yamauchi, H., O’uchi, S., Liu, Y., Tsukada, J., Ishii, K., Sakamoto, K., Suzuki, E., Masahara, M.: Fluctuation analysis of parasitic resistance in FinFETs with scaled fin thickness. Electron Dev. Lett. 30, 407–409 (2009)
Acknowledgment
This work was supported in part by the Taiwan National Science Council (NSC), under Contracts NSC-101-2221-E-009-092, NSC-100-2221-E-009-018, and NSC-99-2221-E-009-175, and by Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, under a 2011-2013 grant.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Cheng, HW., Li, Y. (2013). Characteristic and Fluctuation of Multi-fin FinFETs. In: Han, W., Wang, Z. (eds) Toward Quantum FinFET. Lecture Notes in Nanoscale Science and Technology, vol 17. Springer, Cham. https://doi.org/10.1007/978-3-319-02021-1_6
Download citation
DOI: https://doi.org/10.1007/978-3-319-02021-1_6
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-02020-4
Online ISBN: 978-3-319-02021-1
eBook Packages: Physics and AstronomyPhysics and Astronomy (R0)