Skip to main content
SpringerLink
Log in
Book cover

Toward Quantum FinFET pp 99–124Cite as

Physical Insight and Correlation Analysis of Finshape Fluctuations and Work-Function Variability in FinFET Devices

  • Chapter
  • First Online:

  • 2472 Accesses

Part of the book series: Lecture Notes in Nanoscale Science and Technology ((LNNST,volume 17))

Abstract

One of the major challenges that technology evolution has been facing in the last few years is the increasing severity of variability associated with the discrete nature of charge and the atomicity of matter, which become relevant in aggressively scaled devices. This is even more critical as device architecture has evolved from the conventional planar CMOS technology into three-dimensional multi-gate structures such as FinFETs. The 3D nature of FinFETs is reflected in an enhanced impact of geometry fluctuations in various dimensions: line-edge roughness (LER) in these devices affects both the top and sidewall gate profiles, as well as the fin thickness. Furthermore, different orientations of metal grains which appear in modern metal-gate electrodes result in undesired work-function variations (WFV). The impact of LER and WFV on FinFET electrical performance is studied in this chapter through extensive Monte Carlo (MC) ensemble simulations compared with simplified models for variability estimation. Relevant electrical parameters are correlated with representative descriptors of the various roughness or gate granularity configurations. The analysis provides insight on the physical phenomena that cause fluctuations as well as indication on critical device features to be optimized for improved variation tolerance. The presented investigation has general validity and its conclusions are expected to apply to both current and future generations of multi-gate devices.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD   109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. Arnaud, F., Liu, J., Lee, Y.M., Lim, S., Chen, J., Moon, B.K., Lai, C.W., Lipinski, M., Sang, L., Guarin, F., Hobbs, C., Ferreira, P., Ohuchi, K., Li, J., Zhuang, H., Mora, P., Zhang, Q., Nair, D.R., Lee, D.H., Chan, K.K., Satadru, S., Yang, S., Koshy, J., Hayter, W., Zaleski, M., Coolbaugh, D.V., Kim, H.W., Ee, Y.C., Sudijono, J., Thean, A., Sherony, M., Samavedam, S., Khare, M., Goldberg, C., A.Steegen: 32nm general purpose bulk CMOS technology for high performance applications at low voltage. In: IEDM Tech. Dig. (2008)

    Google Scholar 

  2. Asenov, A.: Random dopant induced threshold voltage lowering and fluctuations in sub 0.1 micron MOSFETs: a 3D ‘atomistic’ simulation study. IEEE Trans. Electron Dev. 45, 2505–2513 (1998)

    Google Scholar 

  3. Asenov, A., Brown, A.R., Davies, J.H., Kaya, S., Slavcheva, G.: Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs. IEEE Trans. Electron Dev. 50(9), 1837–1852 (2003)

    Article  ADS  Google Scholar 

  4. Asenov, A., Brown, A.R., Roy, G., Cheng, B., Alexander, C., Riddet, C., Kovac, U., Martinez, A., Seoane, N., Roy, S.: Simulation of statistical variability in nano-CMOS transistors using drift-diffusion, Monte Carlo and non-equilibrium Greens function techniques. J. Comput. Electron. 8, 349–373 (2009)

    Google Scholar 

  5. Asenov, A., Cathignol, A., Cheng, B., McKenna, K.P., Brown, A.R., Shluger, A.L., Chanemougame, D., Rochereau, K., Ghibaudo, G.: Origin of the asymmetry in the magnitude of the statistical variability of n- and p-channel Poly-Si gate bulk MOSFETs. IEEE Electron. Dev. Lett. 29(8), 913–915 (2008)

    Article  ADS  Google Scholar 

  6. Asenov, A., Kaya, S.: Effect of oxide interface roughness on the threshold voltage fluctuations in decanano MOSFETs with ultrathin gate oxides. In: Proc. SISPAD, pp. 135–138 (2000)

    Google Scholar 

  7. Asenov, A., Kaya, S., Brown, A.R.: Intrinsic parameter fluctuations in decananometer MOSFETs induced by gate line edge roughness. IEEE Trans. Electron Dev. 50(5), 1254–60 (2003)

    Article  ADS  Google Scholar 

  8. Auth, C., Allen, C., Blattner, A., Bergstrom, D., Brazier, M., Bost, M., Buehler, M., Chikarmane, V., Ghani, T., Glassman, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., Hentges, P., Heussner, R., Hicks, J., Ingerly, D., Jain, P., Jaloviar, S., James, R., Jones, D., Jopling, J., Joshi, S., Kenyon, C., Liu, H., McFadden, R., McIntyre, B., Neirynck, J., Parker, C., Pipes, L., Post, I., Pradhan, S., Prince, M., Ramey, S., Reynolds, T., Roesler, J., Sandford, J., Seiple, J., Smith, P., Thomas, C., Towner, D., Troeger, T., Weber, C., Yashar, P., Zawadzki, K., Mistry, K.: A 22nm high performance and low-power cmos technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density mim capacitors. In: VLSI Tech. Dig., pp. 131–132 (2012)

    Google Scholar 

  9. Baravelli, E., De Marchi, L., Speciale, N.: Fin shape fluctuations in FinFET: correlation to electrical variability and impact on 6-T SRAM noise margins. Solid State Electron. 53(12), 1303–1312 (2009)

    Article  ADS  Google Scholar 

  10. Baravelli, E., Dixit, A., Rooyackers, R., Jurczak, M., Speciale, N., De Meyer, K.: Impact of line-edge roughness on FinFET matching performance. IEEE Trans. Electron Dev. 54(9), 2466–2474 (2007)

    Article  ADS  Google Scholar 

  11. Baravelli, E., Jurczak, M., Speciale, N., De Meyer, K., Dixit, A.: Impact of LER and random dopant fluctuations on FinFET matching performance. IEEE Trans. Nanotechnology 7(3), 291–8 (2008)

    Article  ADS  Google Scholar 

  12. Brown, A.R., Roy, G., Asenov, A.: Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture. IEEE Trans. Electron Dev. 54(11), 3056–3063 (2007)

    Article  ADS  Google Scholar 

  13. Dadgour, H., De, V., Banerjee, K.: Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. In: Proc. ICCAD, pp. 270–277 (2008)

    Google Scholar 

  14. Dixit, A., Anil, K.G., Baravelli, E., Roussel, P., Mercha, A., Gustin, C., Bamal, M., Grossar, E., Rooyackers, R., Augendre, E., Jurczak, M., Biesemans, S., De Meyer, K.: Impact of stochastic mismatch on measured SRAM performance of FinFETs with resist/spacer-defined fins: Role of line-edge-roughness. In: IEDM Tech. Dig. (2006)

    Google Scholar 

  15. Dixit, A., Anil, K.G., Collaert, N., Goodwin, M., Jurczak, M., De Meyer, K.: Analysis of the parasitic S/D resistance in multiple-gate FETs. IEEE Trans. Electron Dev. 52(6), 1132–40 (2005)

    Article  ADS  Google Scholar 

  16. He, J.L., Setsuhara, Y., Shimizu, I., Miyake, S.: Structure refinement and hardness enhancement of titanium nitride films by addition of copper

    Google Scholar 

  17. ITRS: http://public.itrs.net

  18. Kovac, U., Reid, D., Millar, C., Roy, G., Roy, S., Asenov, A.: Statistical simulation of random dopant induced threshold voltage fluctuations for 35nm channel length MOSFET. Microelectron. Reliab. 48(8-9), 1572–1575 (2008)

    Article  Google Scholar 

  19. Li, Y., Hwang, C.H., Li, T.Y., Han, M.H.: Proces-variation effects, metal-gate work-function fluctuation, and random-dopant fluctuation in emerging CMOS technologies. IEEE Trans. Electron Dev. 57(2), 437–447 (2010)

    Article  ADS  Google Scholar 

  20. Lundstrom, M., Ren, Z.: Essential physics of carrier transport in nanoscale MOSFETs. IEEE Trans. Electron Dev. 49(1), 133–41 (2002)

    Article  ADS  Google Scholar 

  21. Matsukawa, T., Liu, Y., Mizubayashi, W., Tsukada, J., Yamauchi, H., Endo, K., Ishikawa, Y., O’uchi, S., Ota, H., Migita, S., Morita, Y., Masahara, M.: Suppressing V t and G m variability of FinFETs using amorphous metal gates for 14 nm and beyond. In: IEDM Tech. Dig., pp. 175–178 (2012)

    Google Scholar 

  22. Mérelle, T., Curatola, G., Nackaert, A., Collaert, N., van Dal, M., Doornbos, G., Doorn, T., Christie, P., Vellianitis, G., Duriez, B., Duffy, R., Pawlak, B., Voogt, F., Rooyackers, R., Witters, L., Jurczak, M., Lander, R.: First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling. In: IEDM Tech. Dig. (2008)

    Google Scholar 

  23. Mistry, K., Allen, C., Auth, C., Beattie, B., D. Bergstrom and, M.B., Brazier, M., Buehler, M., Cappellani, A., Chau, R., Choi, C.H., Ding, G., Fischer, K., Ghani, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., He, J., Hicks, J., Huessner, R., Ingerly, D., Jain, P., James, R., Jong, L., Joshi, S., Kenyon, C., Kuhn, K., Lee, K., Liu, H., Maiz, J., McIntyre, B., Moon, P., Neirynck, J., Pae, S., Parker, C., Parsons, D., Prasad, C., Pipes, L., Prince, M., Ranade, P., Reynolds, T., Sandford, J., Shifren, L., Sebastian, J., Seiple, J., Simon, D., Sivakumar, S., Smith, P., Thomas, C., Troeger, T., Vandervoorn, P., Williams, S., Zawadzki, K.: A 45nm logic technology with High-k+Metal Gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging. In: IEDM Tech. Dig., pp. 247–50 (2007)

    Google Scholar 

  24. Mizuno, T., Okamura, J., Toriumi, A.: Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs. IEEE Trans. Electron Dev. 41(11), 22162221 (1994)

    Article  Google Scholar 

  25. Ohmori, K., Matsuki, T., Ishikawa, D., Morooka, T., Aminaka, T., Sugita, Y., Chikyow, T., Shiraishi, K., Nara, Y., Yamada, K.: Impact of additional factors in threshold voltage variability of Metal/High-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates. In: IEDM Tech. Dig. (2008)

    Google Scholar 

  26. Oldiges, P., Lint, Q., Petrillot, K., Sanchez, M., Ieong, M., Hargrove, M.: Modeling line edge roughness effects in sub 100 nanometer gate length devices. In: Proc. SISPAD, pp. 131–4 (2000)

    Google Scholar 

  27. Sentaurus Device Manual: Synopsys, Inc.

    Google Scholar 

  28. Serra, N., Palestri, P., Smit, G., Selmi, L.: Multi-subband Monte Carlo simulations of I ON degradation due to fin thickness fluctuations in FinFETs. Solid State Electron. 53(4), 424–32 (2009)

    Article  ADS  Google Scholar 

  29. Skotnicki, T., Fenouillet-Beranger, C., Gallon, C., Boeuf, F., Monfray, S., Payet, F., Pouydebasque, A., Szczap, M., Farcy, A., Arnaud, F., Clerc, S., Sellier, M., Cathignol, A., Schoellkopf, J.P., Perea, E., Mingam, R.F.H.: Innovative materials, devices, and CMOS technologies for low-power mobile multimedia. IEEE Trans. Electron Dev. 55(1), 96–130 (2008)

    Article  Google Scholar 

  30. Subramanian, V., Mercha, A., Parvais, B., Loo, J., Gustin, C., Dehan, M., Collaert, N., Jurczak, M., Groeseneken, G., Sansen, W., Decoutere, S.: Impact of fin width on digital and analog performances of n-FinFETs. Solid State Electron. 51(4), 551–9 (2007)

    Article  ADS  Google Scholar 

  31. Wang, X., Brown, A., Cheng, B., Asenov, A.: Statistical variability and reliability in nanoscale finfets. In: IEDM Tech. Dig., pp. 5.4.1–5.4.4 (2012)

    Google Scholar 

  32. Xiong, S., Bokor, J.: Sensitivity of double-gate and FinFET devices to process variations. IEEE Trans. Electron Dev. 50(11), 2255–61 (2003)

    Article  ADS  Google Scholar 

  33. Yagishita, A., Saito, T., Nakajima, K., Inumiya, S., Matsuo, K., Shibata, T., Tsunashima, Y., Suguro, K., Arikado, T.: Improvement of threshold voltage deviation in damascene metal gate transistors. IEEE Trans. Electron Dev. 48(8), 1604–1611 (2001)

    Article  ADS  Google Scholar 

  34. Yu, S., Zhao, Y., Song, Y., Du, G., Kang, J., Han, R., Liu, X.: 3-D simulation of geometrical variations impact on nanoscale FinFETs. In: Proc. ICSICT, pp. 408–11 (2008)

    Google Scholar 

  35. Zhang, X., Li, J., Grubbs, M., Deal, M., Magyari-Köpe, B., Clemens, B.M., Nishi, Y.: Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implications for SRAM reliability. In: IEDM Tech. Dig., pp. 3.4.1–3.4.4 (2009)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. University of Bologna, Viale Risorgimento, 2, 40136, Bologna, Italy

    Emanuele Baravelli

Authors
  1. Emanuele Baravelli
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Emanuele Baravelli .

Editor information

Editors and Affiliations

  1. Engineering Research Center for Semiconductor Integrated Technology, Chinese Academy of Sciences, Beijing, People's Republic of China

    Weihua Han

  2. Engineering Research Center for Semiconductor Integrated Technology, Chinese Academy of Sciences, Beijing, People's Republic of China

    Zhiming M. Wang

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Baravelli, E. (2013). Physical Insight and Correlation Analysis of Finshape Fluctuations and Work-Function Variability in FinFET Devices. In: Han, W., Wang, Z. (eds) Toward Quantum FinFET. Lecture Notes in Nanoscale Science and Technology, vol 17. Springer, Cham. https://doi.org/10.1007/978-3-319-02021-1_5

Download citation

Publish with us

Policies and ethics

Search

Navigation