Abstract
This chapter highlights the importance of drain extended class of high voltage MOS devices for advanced implementations of System on Chip (SoC) applications using FinFET or other tri-gate technologies. The working principle of drain extended MOS device is explained and an understanding is built in order to bridge existing drain extended planar devices and future drain extended, FinFETs or tri-gate devices. In this connection, a recently proposed Drain extended FinFET device is discussed for high voltage as well as high speed applications. This shows a better RON vs. V BD trade-off when compared to a conventional device option. Finally, device design and optimization guidelines have been discussed for the new drain extended FinFET device.
Mayank Shrivastava was formerly with Intel Corp., Mobile and Communications Group, Munich, Germany.
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Shrivastava, M., Gossner, H., Rao, V.R. (2013). Towards Drain Extended FinFETs for SoC Applications. In: Han, W., Wang, Z. (eds) Toward Quantum FinFET. Lecture Notes in Nanoscale Science and Technology, vol 17. Springer, Cham. https://doi.org/10.1007/978-3-319-02021-1_10
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