Abstract
After the successful launch of K-Computer in Japan, the Japanese government started a new R&D program entitled “Feasibility Study of Future HPCI Systems.” In this program, social and scientific demands for HPC in the next 5–10 years will be addressed, and HPC systems that satisfy the demands and key technologies to develop such systems will be discussed and evaluated. Currently, three system design teams get involved in this program, and this article present a HPC project entitled “Feasibility Study of Future HPC Systems for Memory Intensive Applications,” which is conducted by a team of Tohoku University, JAMSTEC and NEC.
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Acknowledgements
Many colleagues get involved in this project, and great thanks go to Dr. Y. Kaneda and Dr. K. Watanabe of JAMSTEC (Japan Agency for Marine-Earth Science and Technology) as co-leaders of the application group, Professor M. Koyanagi of Tohoku University as the leader of the 2.5D/3D device group, and Ms. Y. Hashimoto of NEC as the leader of the NEC application, system and device design group. This project is supported by MEXT.
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Kobayashi, H. (2013). Feasibility Study of Future HPC Systems for Memory-Intensive Applications. In: Resch, M., Bez, W., Focht, E., Kobayashi, H., Kovalenko, Y. (eds) Sustained Simulation Performance 2013. Springer, Cham. https://doi.org/10.1007/978-3-319-01439-5_1
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DOI: https://doi.org/10.1007/978-3-319-01439-5_1
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