Testing of MOSFETs Surfaces Using Image Acquisition

  • Viranjay M. Srivastava
  • Ghanshyam Singh
Part of the Analog Circuits and Signal Processing book series (ACSP, volume 122)


The image processing is frequently used in the systems for monitoring and controlling of the objects to support in an effective management of their resources and safety. The practical systems for monitoring the rectangular objects, like DG MOSFET, and cylindrical objects like CSDG MOSFET, which requires various vision sensors, recording images that have to be transmitted to and processed in the central processing unit [1]. One of the most challenging problems in such cases is the effective transmission and processing of huge amount of image data. To avoid overloading of transmission channels and central unit, various already existing algorithms are frequently performed at the sensors by an integrated low-level image processor. As a result, the rough image data generated by the sensor can be compressed or replaced by useful information extracted from the images. This approach significantly improves the overall efficiency and the cost of the system. A complete vision chip consisting of a photodetector array, which is effectively implemented on DG MOSFET and CSDG MOSFET, is formed on the rectangular and cylindrical substrate, respectively [2].


Discrete Fourier Transform Image Sensor Vision Sensor Filter Function Single Instruction Multiple Data 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    P. Dutkiewicz, M. Kieczewski, K. Kozowski, and D. Pazderski, “Vision localization system for mobile robot with velocities and acceleration estimator,” Bulletin of the Polish Academy of Sciences and Technical Sciences, vol. 58, no. 1, pp. 29–41, Dec. 2010.Google Scholar
  2. 2.
    W. Jendernalik, J. Jakusz, G. Blakiewicz, R. Piotrowski, and S. Szczepanski, “CMOS realisation of analogue processor for early vision processing,” Bulletin of the Polish Academy of Sciences and Technical Sciences, vol. 59, no. 2, pp. 141-147, Aug. 2011.Google Scholar
  3. 3.
    R. E. Cummings, Z. K. Kalayjian, and D. Cai, “A programmable focal plane MIMD image processor chip,” IEEE J. Solid State Circuits, vol. 36, no. 1, pp. 64–73, Jan. 2001.CrossRefGoogle Scholar
  4. 4.
    J. Schemmel, K. Meier, and M. Loose, “A scalable switched capacitor realization of the resistive fuse network,” Analog Integrated Circuits and Signal Processing, vol. 32, no. 2, pp. 135–148, Aug. 2002.CrossRefGoogle Scholar
  5. 5.
    A. Dupret, J. O. Klein, and A. Nshare, “A DSP-like analog processing unit for smart image sensors,” Int. J. Circuit Theory and Application, vol. 30, no. 6, pp. 595–609, 2002.CrossRefzbMATHGoogle Scholar
  6. 6.
    D. A. Martin, H. S. Lee, and I. Masaki, “A mixed signal array processor with early vision applications,” IEEE J. Solid State Circuits, vol. 33, no. 3, pp. 497–502, March 1998.CrossRefGoogle Scholar
  7. 7.
    P. Dudek and P. J. Hicks, “An analogue SIMD focal plane processor array,” Proc. of IEEE Int. Symp. on Circuits and Systems, Sydney, Australia, 6-9 May 2001, pp. 490–493.Google Scholar
  8. 8.
    P. Dudek and P. J. Hicks, “A general purpose processor per-pixel analog SIMD vision chip,” IEEE Trans. Circuits and Systems, vol. 52, no. 1, pp. 13–20, Jan. 2005.CrossRefGoogle Scholar
  9. 9.
    P. Dudek, A. Lopich, and V. Gruev, “A pixel parallel cellular processor array in a stacked three layer 3D silicon-on-insulator technology,” Proc. of Eur. Conf. on Circuit Theory and Design, Turkey, Antalya, 23–27 Aug. 2009, pp. 193–196.Google Scholar
  10. 10.
    V. Suntharalingam, R. Berger, J. Bums, and C. Chen, “Megapixel CMOS image sensor fabricated in three dimensional integrated circuit technology,” Proc. of IEEE Solid State Circuits Conf., Pennsylvania, USA, 10 Feb. 2005, pp. 356-357.Google Scholar
  11. 11.
    E. Culurciello and P. Weerakoon, “Three dimensional photo detectors in 3D silicon-on-insulator technology,” IEEE Electron Device Letters, vo1. 28, pp.117-119, 2007.Google Scholar
  12. 12.
    G. Blakiewicz, “Analog multiplier for a low-power integrated image sensor,” 16 th Int. Conf. on Mixed Design of Integrated Circuits and Systems, Poland, 25-27 June 2009, pp. 226-229.Google Scholar
  13. 13.
    P. Dollfus, “Sensitivity of single and double-gate MOS architectures to residual discrete dopant distribution in the channel,” J. of Computational Electronics, vol. 5, no. 2-3, pp. 119-123, July 2006.Google Scholar
  14. 14.
    Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch,” Microelectronics Journal, vol. 42, no. 10, pp. 1124-1135, Oct. 2011.Google Scholar
  15. 15.
    Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Analysis of double gate CMOS for DP4T RF switch design at 45-nm technology,” J. of Computational Electronics, vol. 10, no. 1-2, pp. 229-240, June 2011.Google Scholar
  16. 16.
    M. Cheralathan, Antonio Cerdeira, and Benjamin Iniguez, “Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations,” Solid State Electronics, vol. 55, no. 1, pp. 13-18, Jan. 2011.CrossRefGoogle Scholar
  17. 17.
    S. Kolberg, H. Borli, and T. A. Fjeldly, “Modeling, verification and comparison of short-channel double gate and gate-all-around MOSFETs,” Mathematics and Computers in Simulation, vol. 79, no. 4, pp. 1107-1115, Dec. 2008.MathSciNetCrossRefzbMATHGoogle Scholar
  18. 18.
    M. Reyboz, P. Martin, T. Poiroux, and O. Rozeau, “Continuous model for independent double gate MOSFET,” Solid State Electronics, vol. 53, no. 5, pp. 504-513, May 2009.CrossRefGoogle Scholar
  19. 19.
    Riza Tamer and Kausik Roy, “Analysis of options in double-gate MOS technology: A circuit perspective,” IEEE Trans. on Electron Devices, vol. 54, no. 12, pp. 3361–3368, Dec. 2007.Google Scholar
  20. 20.
    Antonio Cerdeira, Benjamin Iniguez, and Magali Estrada, “Compact model for short channel symmetric doped double-gate MOSFETs,” Solid State Electronics, vol. 52, no. 7, pp. 1064-1070, July 2008.CrossRefGoogle Scholar
  21. 21.
    A. G. Andreou, R. C. Meitzler, K. Strohbehn, and K. A. Boahen, “Analog VLSI neuromorphic image acquisition and pre-processing systems,” Neural Networks, vol. 8, no. 7–8, pp. 1323-1347, 1995.CrossRefGoogle Scholar
  22. 22.
    M. Furumiya, “High sensitivity and no-crosstalk pixel technology for embedded CMOS image sensor,” IEEE Trans. Electron Devices, vol. 48, no. 10, pp. 2221–2227, Oct. 2001.Google Scholar
  23. 23.
    P. Gonthier, E. Havard, and P. Magnan, “Custom transistor layout design techniques for random telegraph signal noise reduction in CMOS image sensors,” Electronics Letters, vol. 46, no. 19, pp. 1323-1324, Sept. 2010Google Scholar
  24. 24.
    Maria Petrou, and Panagiota Bosdogianni, Image processing: The fundamental, John Wiley & Sons Ltd, New York, 2000.Google Scholar
  25. 25.
    Rafael C. Gonzalez, and Richard E. Woods, Digital Image Processing, 2nd Edition, Prentice-Hall of India, New Delhi, 2002.Google Scholar
  26. 26.
    Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Explicit model of cylindrical surrounding double-gate MOSFETs,” WSEAS Trans. on Circuits and Systems, vol. 12, no. 3, pp. 81–90, March 2013.Google Scholar
  27. 27.
    C. Rubat Du Merac, P. Jutier, J. Laurent, and B. Courtois, “A new domain for image analysis: VLSI circuits testing, with Romuald, specialized in parallel image processing,” Pattern Recognition Letters, vol. 1, no. 5–6, pp. 347-352, July 1983.CrossRefGoogle Scholar
  28. 28.
    A. Gamal and H. Eltoukhy, “CMOS image sensors,” IEEE Circuits and Devices Magazine, vol. 21, no. 3, pp. 6–20, March 2005.CrossRefGoogle Scholar
  29. 29.
    Jiaming Tan, B. Buttgen, and A. Theuwissen, “Analyzing the radiation degradation of 4-transistor deep submicron technology CMOS image sensors,” IEEE Sensors J., vol. 12, no. 6, pp. 2278-2286, June 2012.CrossRefGoogle Scholar
  30. 30.
    H. D. Cheng, Y. Y. Tang, and C. Y. Suen, “Parallel image transformation and its VLSI implementation,” Pattern Recognition, vol. 23, no. 10, pp. 1113-1129, 1990.CrossRefGoogle Scholar
  31. 31.
    International Technology Roadmap for Semiconductors-2010,
  32. 32.
    Ching Hsien Chang, Chin Liang Wang, and Yu Tai Chang, “Efficient VLSI architectures for fast computation of the discrete Fourier transform and its inverse,” IEEE Trans. on Signal Processing, vol. 48, no. 11, pp. 3206-3216, Nov. 2000.Google Scholar
  33. 33.
    L. D. Van, Yuan Chu Yu, Chun Ming Huang, and Chin Teng Lin, “Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture,” Proc. IEEE Workshop on Signal Processing Systems Design and Implementation, Athens, Greece, 2–4 Nov. 2005, pp. 579- 584.Google Scholar
  34. 34.
    Haidi Ibrahim and Nicholas Kong, “Image sharpening using sub-regions histogram equalization,” IEEE Trans. on Consumer Electronics, vol. 55, no. 2, pp. 891-895, May 2009.Google Scholar
  35. 35.
    A. G. Corry, D. K. Arvind, G. S. Connolly, R. R. Korya, and I. N. Parker, “Image processing with VLSI,” Microprocessors and Microsystems, vol. 7, no. 10, pp. 482-486, Dec. 1983.CrossRefGoogle Scholar
  36. 36.
    Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “DP4T RF CMOS switch: A better option to replace SPDT switch and DPDT switch,” Recent Patents on Electrical and Electronic Engineering, vol. 5, no. 3, pp. 244–248, Oct. 2012.Google Scholar
  37. 37.
    Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Drain current and noise model of cylindrical surrounding double-gate MOSFET for RF switch,” Procedia Engineering, vol. 38, pp. 517–521, April 2012.Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Viranjay M. Srivastava
    • 1
  • Ghanshyam Singh
    • 1
  1. 1.Department of Electronics and Communication EngineeringJaypee University of Information TechnologySolanIndia

Personalised recommendations