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Cylindrical Surrounding Double-Gate RF MOSFET

  • Viranjay M. Srivastava
  • Ghanshyam Singh
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP, volume 122)

Abstract

To reduce the size and increase the compactness in terms of area for the designed double-gate (DG) MOSFET as discussed in Chap. 3, we have analyzed and model the gate all around the DG MOSFET and in this chapter we have designed the cylindrical surrounding double-gate (CSDG) MOSFET and analyzed the design parameters of this MOSFET as a RF switch for the advanced wireless telecommunication systems. We have emphasized on the basics of the circuit parameters such as drain current, threshold voltage, resonant frequency, resistances at switch ON-state condition, capacitances, energy stored, cross talk, and switching speed required for the integrated circuit of the radio frequency subsystem of the CSDG MOSFET device and physical significance of these basic circuit parameters are also discussed. We have analyzed the CSDG MOSFET stored more energy (1.4 times) as compared to the cylindrical surrounding single-gate (CSSG) MOSFET. The ON-state resistance of CSDG MOSFET is half as compared to the DG MOSFET and SG MOSFET, which reveals that the current flow from source to drain in CSDG MOSFET is better than that of the DG MOSFET and SG MOSFET.

Keywords

Threshold Voltage Drain Current Flicker Noise Subthreshold Swing Short Channel Effect 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    S. Ahmed, C. Ringhofer, and D. Vasileska, “An effective potential approach to modeling 25 nm MOSFET devices,” J. of Computational Electronics, vol. 9, no. 3–4, pp. 197–200, Oct. 2010.Google Scholar
  2. 2.
    Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Analysis of drain current and switching speed for SPDT switch and DPDT switch with the proposed DP4T RF CMOS switch,” J. of Circuits, Systems and Computers, vol. 21, no. 4, pp. 1–18, June 2012.Google Scholar
  3. 3.
    Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF Switch,” Microelectronics Journal, vol. 42, no. 3, pp. 527–534, March 2011.Google Scholar
  4. 4.
    International Technology Roadmap for Semiconductors-2010, www.public.itrs.net
  5. 5.
    S. Cristoloveanu and S. S. Li, Electrical Characterization of SOI Materials and Devices, Kluwer Publications, Massachusetts, USA, 1995.Google Scholar
  6. 6.
    N. Ashraf and D. Vasileska, “1/f Noise: threshold voltage and ON-current fluctuations in 45-nm device technology due to charged random traps,” J. of Computational Electronics, vol. 9, no. 3–4, pp. 128–134, Oct. 2010.Google Scholar
  7. 7.
    K. Takeuchi, T. Fukai, A. Nishida, and T. Hiramoto, “Understanding random threshold voltage fluctuation by comparing multiple fabs and technologies,” Proc. of IEEE Int. Electron Device Meeting, Washington, DC, USA, 10–12 Dec. 2007, pp. 467–470.Google Scholar
  8. 8.
    Yang Tang, Li Zhang, and Yan Wang, “Accurate small signal modeling and extraction of silicon MOSFET for RF IC application,” Solid State Electronics, vol. 54, no. 11, pp. 1312–1318, Nov. 2010.Google Scholar
  9. 9.
    R. H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: from bulk to SOI to bulk,” IEEE Trans. on Electron Devices, vol. 39, no. 7, pp. 1704–1710, July 1992.Google Scholar
  10. 10.
    A. Nitayami, H. Takato, N. Okabe, K. Sunouchi, K. Hiea, and F. Horiguchi, “Multipillar surrounding gate transistor (M-SGT) for compact and high-speed circuits,” IEEE Trans. on Electron Devices, vol. 38, no. 3, pp. 579–583, March 1991.Google Scholar
  11. 11.
    S. Watanabe, K. Tsuchida, D. Takashima, Y. Oowaki, A. Nitayama, and K. Hieda, “A novel circuit technology with surrounding gate transistors (SGT’s) for ultra high density DRAM’s,” IEEE J. Solid State Circuits, vol. 30, no. 9, pp. 960–971, Sept. 1995.Google Scholar
  12. 12.
    L. Ge and Jerry G. Fossum, “Analytical modeling of quantization and volume inversion in thin Si film DG MOSFETs,” IEEE Trans. on Electron Devices, vol. 49, no. 2, pp. 287–294, Feb. 2002.Google Scholar
  13. 13.
    A. Rahman and M. S. Lundstrom, “A compact scattering model for the nanoscale double-gate MOSFET,” IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 481–489, March 2002.Google Scholar
  14. 14.
    F. Djeffal, Z. Ghoggali, Z. Dibi, and N. Lakhdar, “Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot carrier induced interface charges,” Microelectronics Reliability, vol. 49, no. 4, pp. 377–381, April 2009.Google Scholar
  15. 15.
    P. Dollfus, and Retailleau, “Thermal noise in nanometric DG MOSFET,” J. of Computational Electronics, vol. 5, no. 4, pp. 479–482, Dec. 2006.Google Scholar
  16. 16.
    P. Dollfus, “Sensitivity of single and double-gate MOS architectures to residual discrete dopant distribution in the channel,” J. of Computational Electronics, vol. 5, no. 2–3, pp. 119–123, Sept. 2006.Google Scholar
  17. 17.
    S. Sharma and P. Kumar, “Non overlapped single and double gate SOI/GOI MOSFET for enhanced short channel immunity,” J. of Semiconductor Technology and Science, vol. 9, no. 3, pp. 136–147, Sept. 2009.Google Scholar
  18. 18.
    A. Kranti, Y. Hao and G. A. Armstrong, “Performance projections and design optimization of planar double-gate SOI MOSFETs for logic technology applications,” Semiconductor Science and Technology, vol. 23, no. 4, pp. 1–13, 2008.Google Scholar
  19. 19.
    T. C. Lim and G. A. Armstrong, “Scaling issues for analogue circuits using double gate SOI transistors,” Solid State Electronics, vol. 51, no. 2, pp. 320–327, Feb. 2007.Google Scholar
  20. 20.
    Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd Edition, Cambridge University Press, USA, 2004.Google Scholar
  21. 21.
    D. Rechem, S. Latreche, and C. Gontrand, “Channel length scaling and the impact of metal-gate work function on the performance of double-gate MOSFETs,” J. of Physics, vol. 72, no. 3, pp. 587–599, March 2009.Google Scholar
  22. 22.
    S. Amakawa, K. Nakazato, and H. Mizuta, “A surface potential based cylindrical surrounding gate MOSFET model,” Proc. of Int. Conf. on Solid State Devices and Materials, Tokyo, Japan, 16–18 Sept. 2003, pp. 1–2.Google Scholar
  23. 23.
    Cong Li, Yiqi Zhuang, and Ru Han, “Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension,” Microelectronics Journal, vol. 42, no. 2, pp. 341–346, Feb. 2011.Google Scholar
  24. 24.
    Te Kuang Chiang, “Concise analytical threshold voltage model for cylindrical fully depleted surrounding-gate MOSFET,” Jpn. J. Appl. Phys., vol. 44, no. 5, pp. 2948–2952, 2005.Google Scholar
  25. 25.
    H. Kaur, S. Kabra, S. Bindra, S. Haldar, and R. Gupta, “Impact of graded channel design in fully depleted cylindrical/surrounding gate MOSFET for improved short channel immunity and hot carrier reliability,” Solid State Electronics, vol. 51, no. 3, pp. 398–404, March 2007.Google Scholar
  26. 26.
    Mei Chao Yeh, Zuo Min Tsai, and Huei Wang, “A miniature DC to 50 GHz CMOS SPDT distributed switch,” Proc. of European Symp. on Gallium Arsenide and Other Semiconductor Application, Paris, 3–4 Oct. 2005, pp. 665–668.Google Scholar
  27. 27.
    Huaxin Lu, Wei Yuan Lu, and Yuan Taur, “Effect of body doping on double-gate MOSFET characteristics,” Semiconductor Science and Technology, vol. 23, no. 1, pp. 1–6, Jan. 2008.Google Scholar
  28. 28.
    Oana Moldovan, Ferney A. Chaves, David Jimenez, Jean P. Raskin, and Benjamin Iniguez, “Accurate prediction of the volume inversion impact on undoped double-gate MOSFET capacitances,” Int. J. of Numerical Modeling: Electronic Networks, Devices and Fields, vol. 23, no. 6, pp. 447–457, Nov. 2010.Google Scholar
  29. 29.
    C. Y. Lin, M. W. Ma, A. Chin, Y. C. Yeo, and D. L. Kwong, “Fully silicided NiSi gate on La2O3 MOSFETs,” IEEE Electron Device Letter, vol. 24, no. 5, pp. 348–350, May 2003.Google Scholar
  30. 30.
    J. Liu, H. C. Wen, J. P. Lu, and D. L. Kwong, “Dual work-function metal gates by full silicidation of poly-Si with Co-Ni bi-layers,” IEEE Electron Device Letter, vol. 26, no. 4, pp. 228–230, April 2005.Google Scholar
  31. 31.
    I. V. Singh and M. S. Alam, “Single-gate and double-gate SOI MOSFET structures and compression of electrical performance,” Int. J. of Computer Applications, vol. 17, pp. 5–11, Oct. 2010.Google Scholar
  32. 32.
    T. Li, C. Hu, W. Ho, H. Wang, and C. Chang, “Continuous and precise work function adjustment for integratable dual metal gate CMOS technology using Hf-Mo binary alloys,” IEEE Trans. on Electron Devices, vol. 52, no. 6, pp. 1172–1179, June 2005.Google Scholar
  33. 33.
    C. H. Lu, G. Wong, M. Deal, W. Tsai, P. Majhi, J. Chambers, B. Clemens, and Y. Nishi, “Characteristics and mechanism of tunable work function gate electrodes using a bilayer metal structure on SiO2 and HfO2,” IEEE Electron Device Letter, vol. 26, no. 7, pp. 445–447, July 2005.Google Scholar
  34. 34.
    Yuan Taur, D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, and Hon Sum Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proc. of IEEE, vol. 89, no. 3, pp. 259–288, March 2001.Google Scholar
  35. 35.
    S. Kolberg, H. Borli, and T. A. Fjeldly, “Capacitance modeling of short channel double-gate MOSFETs,” Solid State Electronics, vol. 52, no. 10, pp. 1486–1490, Oct. 2008.Google Scholar
  36. 36.
    Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Analysis of double-gate CMOS for DP4T RF switch design at 45 nm technology,” J. of Computational Electronics, vol. 10, no. 1–2, pp. 229–240, June 2011.Google Scholar
  37. 37.
    M. Cheralathan, Antonio Cerdeira, and Benjamin Iniguez, “Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations,” Solid State Electronics, vol. 55, no. 1, pp. 13–18, Jan. 2011.Google Scholar
  38. 38.
    D. B. Kao, J. P. McVittie, W. D. Nix, and K. C. Saraswat, “Two dimensional thermal oxidation of silicon-I: experiments,” IEEE Trans. on Electron Devices, vol. 34, no. 5, pp. 1008–1017, May 1987.Google Scholar
  39. 39.
    D. B. Kao, J. P. McVittie, W. D. Nix, and K. C. Saraswat, “Two dimensional thermal oxidation of silicon-II: Modeling stress effects in wet oxides,” IEEE Trans. on Electron Devices, vol. 35, no. 1, pp. 25–37, Jan. 1988.Google Scholar
  40. 40.
    Vincent Pott, Kirsten E. Moselund, Didier Bouvet, and Adrian Mihai Ionescu, “Fabrication and characterization of gate-all-around silicon nanowires on bulk silicon,” IEEE Trans. on Nanotechnology, vol. 7, no. 6, pp. 733–744, Nov. 2008.Google Scholar
  41. 41.
    Y. Y. Yeoh, K. H. Yeo, D. W. Kim, S. H. Lee, and C. H. Park, “Characterization of gate-all-around Si-NWFET, including Rsd, cylindrical coordinate based 1/f noise and hot carrier effects,” Proc. of IEEE Int. Reliability Physics Symposium, California, USA, 2–6 May 2010, pp. 94–98.Google Scholar
  42. 42.
    Yun Seop Yu, Namki Cho, Sung Woo Hwang, and Doyeol Ahn, “Analytical threshold voltage model including effective conducting path effect for surrounding-gate MOSFETs with localized charges,” IEEE Trans. on Electron Devices, vol. 57, no. 11, pp. 3176–3180, Nov. 2010.Google Scholar
  43. 43.
    S. Saurabh and M. Kumar, “Impact of strain on drain current and threshold voltage of nanoscale double-gate tunnel field effect transistor: theoretical investigation and analysis,” Jpn. J. Appl. Phys., vol. 48, pp 1–35, June 2009.Google Scholar
  44. 44.
    S. Kolberg, H. Borli, and T. A. Fjeldly, “Modeling, verification and comparison of short channel double-gate and gate-all-around MOSFETs,” Mathematics and Computers in Simulation, vol. 79, no. 4, pp. 1107–1115, Dec. 2008.Google Scholar
  45. 45.
    F. Djeffal, M. Meguellati, and A. Benhaya, “A two dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs,” Physica E: Low dimensional Systems and Nanostructures, vol. 41, no. 10, pp. 1872–1877, Oct. 2009.Google Scholar
  46. 46.
    International Technology Roadmap for Semiconductors-2012, www.public.itrs.net
  47. 47.
    M. Reyboz, P. Martin, T. Poiroux, and O. Rozeau, “Continuous model for independent double-gate MOSFET,” IEEE J. of Solid State Circuits, vol. 53, no. 5, pp. 504–513, May 2009.Google Scholar
  48. 48.
    Ismail Saad and Razali Ismail, “Self aligned vertical double-gate MOSFET with the oblique rotating ion implantation method,” Microelectronics Journal, vol. 39, no. 12, pp. 1538–1541, Dec. 2008.Google Scholar
  49. 49.
    P. Dutta, B. Syamal, N. Mohankumar, and C. K. Sarkar, “A surface potential based drain current model for asymmetric double-gate MOSFETs,” Solid State Electronics, vol. 56, no. 1, pp. 148–154, Feb. 2011.Google Scholar
  50. 50.
    F. Djeffal, M. A. Abdi, D. Arar, and T. Bendib, “An analytical subthreshold swing model to study the scalability limits of double-gate MOSFETs including bulk traps effects,” Proc. of 5 th Int. Conf. on Design and Technology of Integrated Systems in Nanoscale Era, Tunisia, 23–25 March 2010, pp. 1–6.Google Scholar
  51. 51.
    Sungmo Kang and Yusuf Leblebichi, CMOS Digital Integrated Circuits Analysis and Design, 3rd Edition, McGraw-Hill, New York, USA, 2002.Google Scholar
  52. 52.
    Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Application of VEE Pro software for measurement of MOS device parameter using C-V curve,” Int. J. of Computer Applications, vol. 1, no. 7, pp. 43–46, March 2010.Google Scholar
  53. 53.
    Viranjay M. Srivastava, C-V Measurement Using VEE Pro Software after Fabrication of MOS Capacitance, 1st Edition, VDM Publishing House, Mauritius, 2010.Google Scholar
  54. 54.
    F. J. Huang and O. Kenneth, “A 0.5 μm CMOS T/R switch for 900 MHz wireless applications,” IEEE J. of Solid State Circuits, vol. 36, no. 3, pp. 486–492, March 2001.Google Scholar
  55. 55.
    Cong Li, Yiqi Zhuang, and Ru Han, “Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension,” Microelectronics Journal, vol. 42, no. 2, pp. 341–346, Feb. 2011.Google Scholar
  56. 56.
    M. Cheralathan and B. Iniguez, “Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations,” Solid State Electronics, vol. 55, no. 1, pp. 13–18, Jan. 2011.Google Scholar
  57. 57.
    L. Gaionia, M. Manghisonib, L. Rattia, V. Reb, V. Spezialia, and G. Traversib, “Instrumentation for Gate Current Noise Measurements on sub-100 nm MOS Transistors,” Proc. of Topical Workshop on Electronics for Particle Physics, Greece, Athence, 15–19 Sep 2008, pp. 436–440.Google Scholar
  58. 58.
    Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Explicit model of cylindrical surrounding double-gate MOSFETs,” WSEAS Trans. on Circuits and Systems, vol. 12, no. 3, pp. 81–90, March 2013.Google Scholar
  59. 59.
    J. Lee, G. Bosman, K. R. Green, D. Ladwing, “Noise model of gate-leakage current in ultrathin oxide MOSFETs,” IEEE Trans. on Electron Devices, vol. 50, no. 12, pp. 2499–2506, Dec. 2003.Google Scholar
  60. 60.
    A. J. Scholten, L. F. Tiemeijer, R. J. Havens, and V. C. Venezia, “Noise modeling for RF CMOS circuit simulation,” IEEE Trans. on Electron Devices, vol. 50, no. 3, pp. 618–632, March 2003.Google Scholar
  61. 61.
    Khaled Ben Ali, Cesar Roda Neve, Ali Gharsallah, and J. P. Raskin, “Impact of crosstalk into high resistivity silicon substrate on the RF performance of SOI MOSFET,” J. of Telecommunications and Information Technology, vol. 3, no. 4, pp. 93–100, 2010.Google Scholar
  62. 62.
    D. Lederer and J. P. Raskin, “RF performance of a commercial SOI technology transferred onto a passivated HR silicon substrate,” IEEE Trans. on Electron Devices, vol. 55, no. 7, pp. 1664–1671, July 2008.Google Scholar
  63. 63.
    Serge Gidon, “Double-gate MOSFET modeling,” Proc. of the COMSOL Multiphysics User's Conf., Paris, 2005, pp. 1–4.Google Scholar
  64. 64.
    Riza Tamer and Kausik Roy, “Analysis of options in double-gate MOS technology: A circuit perspective,” IEEE Trans. on Electron Devices, vol. 54, no. 12, pp. 3361–3368, Dec. 2007.Google Scholar
  65. 65.
    Yiming Li and Hong Mu Chou, “A comparative study of electrical characteristic on sub 10-nm double-gate MOSFETs,” IEEE Trans. on Nanotechnology, vol. 4, no. 5, pp. 645–647, 2005.Google Scholar
  66. 66.
    Pedram Razavi and Ali Orouji, “Nanoscale triple material double gate MOSFET for improving short channel effects,” Proc. of Int. Conf. on Advances in Electronics and Microelectronics, Valencia, Spain, 29 Sept.-4 Oct. 2008, pp. 11–14.Google Scholar
  67. 67.
    Vaidyanathan Subramanian, “Multiple gate field effect transistor for future CMOS technologies,” IETE Technical Review, vol. 27, no. 6, pp. 446–454, Dec. 2010.Google Scholar
  68. 68.
    Tae Hun Kim, Hoon Jeong, Ki Whan Song, and Han Park, “A new capacitor-less 1 T DRAM cell: Surrounding gate MOSFET with vertical channel,” IEEE Trans. on Nanotechnology, vol. 6, no. 3, pp. 352–357, May 2007.Google Scholar
  69. 69.
    S. Venugopalan, Darsen Lu, Yukiya Kawakami, Peter Lee, Ali Niknejad, and Chenming Hu, “BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations,” Solid State Electronics, vol. 67, no. 1, pp. 79–89, Jan. 2012.Google Scholar
  70. 70.
    Usha Gogineni, Jesus Alamo, and Christopher Putnam, “RF power potential of 45-nm CMOS technology,” Proc. of 10 th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Phoenix, Arizona, USA, 11–13 Jan. 2010, pp. 204–207.Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Viranjay M. Srivastava
    • 1
  • Ghanshyam Singh
    • 1
  1. 1.Department of Electronics and Communication EngineeringJaypee University of Information TechnologySolanIndia

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