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Replacing Different Levels of the Memory Hierarchy with NVMs

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Exploring Memory Hierarchy Design with Emerging Memory Technologies

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 267))

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Abstract

As the first step of exploring the usage of various NVMs in different levels of the memory hierarchy, we compare the NVMs with memories used in the traditional memory hierarchy, as shown in Fig. 2.1.

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References

  1. Kim, C., Burger, D., Keckler, S.: An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. In: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (2002)

    Google Scholar 

  2. Thoziyoor, S., Ahn, J.H., Monchiero, M., Brockman, J.B., Jouppi, N.P.: A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies. SIGARCH Comput. Archit. News 36(3), 51–62 (2008). doi:http://doi.acm.org/10.1145/1394608.1382127

  3. Loi, G.L., Agrawal, B., Srivastava, N., Lin, S.C., Sherwood, T., Banerjee, K.: A Thermally-Aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. In: DAC ’06: Proceedings of the 43rd Annual Conference on Design Automation, pp. 991–996 (2006)

    Google Scholar 

  4. Li, F., Nicopoulos, C., Richardson, T., Xie, Y., Narayanan, V., Kandemir, M.: Design and management of 3D chip multiprocessors using network-in-memory. In: ISCA ’06: Proceedings of the 33rd, Annual International Symposium on Computer Architecture, pp. 130–141 (2006)

    Google Scholar 

  5. Chishti, Z., Powell, M.D., Vijaykumar, T.N.: Distance associativity for high-performance energy-efficient non-uniform cache architectures. In: MICRO 36: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, p. 55 (2003)

    Google Scholar 

  6. Chishti, Z., Powell, M.D., Vijaykumar, T.N.: Optimizing replication, communication, and capacity allocation in CMPs. SIGARCH Comput. Archit. News 33(2), 357–368 (2005)

    Article  Google Scholar 

  7. Kahle, J.A., Day, M.N., Hofstee, H.P., Johns, C.R., Maeurer, T.R., Shippy, D.: Introduction to the cell multiprocessor. IBM J. Res. Dev. 49(4/5), 589–604 (2005)

    Article  Google Scholar 

  8. Kongetira, P., Aingaran, K., Olukotun, K.: Niagara: a 32-way multithreaded SPARC processor. IEEE Micro 25(2), 21–29 (2005)

    Article  Google Scholar 

  9. Magnusson, P.S., Christensson, M., Eskilson, J., Forsgren, D., Hållberg, G., Högberg, J., Larsson, F., Moestedt, A., Werner, B.: Simics: a full system simulation platform. Computer 35(2), 50–58 (2002)

    Article  Google Scholar 

  10. http://www.spec.org

  11. Bienia, C., Kumar, S., Singh, J.P., Li, K.: The parsec benchmark suite: characterization and architectural implications. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation, Techniques (2008)

    Google Scholar 

  12. Skadron, K., Stan, M.R., Sankaranarayanan, K., Huang, W., Velusamy, S., Tarjan, D.: Temperature-aware microarchitecture: Modeling and implementation. ACM Trans. Archit. Code Optim. 1(1), 94–125 (2004). doi:http://doi.acm.org/10.1145/980152.980157

    Google Scholar 

  13. Puttaswamy, K., Loh, G.H.: Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors, pp. 193–204 (2007). doi:http://dx.doi.org/10.1109/HPCA.2007.346197

  14. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations. In: ISCA ’00: Proceedings of the 27th Annual International Symposium on Computer Architecture, pp. 83–94. ACM, New York, NY, USA (2000). doi:http://doi.acm.org/10.1145/339647.339657

  15. Black, B., Annavaram, M., Brekelbaum, N., DeVale, J., Jiang, L., Loh, G.H., McCaule, D., Morrow, P., Nelson, D.W., Pantuso, D., Reed, P., Rupley, J., Shankar, S., Shen, J., Webb, C.: Die stacking (3D) microarchitecture. In: MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 469–479 (2006)

    Google Scholar 

  16. Kgil, T., D’Souza, S., Saidi, A., Binkert, N., Dreslinski, R., Mudge, T., Reinhardt, S., Flautner, K.: PicoServer: Using 3D stacking technology to enable a compact energy efficient chip multiprocessor. Proc. 2006 ASPLOS Conf. 41(11), 117–128 (2006)

    Google Scholar 

  17. Dong, X., Wu, X., Sun, G., Xie, Y., Li, H., Chen, Y.: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In: DAC ’08: Proceedings of the 45th Annual Conference on Design Automation, pp. 554–559 (2008)

    Google Scholar 

  18. Zhang, Y., Yang, J., Gupta, R.: Frequent value locality and value-centric data cache design. SIGPLAN Not. 35(11), 150–159 (2000). doi:http://doi.acm.org/10.1145/356989.357003

  19. Yang, J., Zhang, Y., Gupta, R.: Frequent value compression in data caches. In: Proceedings of MICRO 2000, pp. 258–265. doi:http://doi.acm.org/10.1145/360128.360154

  20. Zhou, P., et al.: Frequent value compression in packet-based noc architectures. In: Proceedings of ASP-DAC 2009, pp. 13–18

    Google Scholar 

  21. Yang, J., Gupta, R.: Energy efficient frequent value data cache design. In: Proceedings of the MICRO 2002, pp. 197–207

    Google Scholar 

  22. Mehrara, M., Austin, T.: Exploiting selective placement for low-cost memory protection. ACM Trans. Archit. Code Optim. 5(3), 1–24 (2008). doi:http://doi.acm.org/10.1145/1455650.1455653

  23. Yang, J., Gupta, R.: Frequent value locality and its applications. ACM Trans. Embed. Comput. Syst. 1(1), 79–105 (2002). doi:http://doi.acm.org/10.1145/581888.581894

    Google Scholar 

  24. Kim, Y., et al.: Atlas: a scalable and high-performance scheduling algorithm for multiple memory controllers. In: Proceedings of HPCA 2010, pp. 1–12 (2010). doi:10.1109/HPCA.2010.5416658

  25. Zhou, P., Zhao, B., Yang, J., Zhang, Y.: A durable and energy efficient main memory using phase change memory technology. In: Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 14–23 (2009). doi:http://doi.acm.org/10.1145/1555754.1555759

  26. Qureshi, M.K., Franceschini, M.M., Lastras-Montano, L.A.: Improving read performance of phase change memories via write cancellation and write pausing. In: Proceedings of HPCA ’10, pp. 123–132 (2010)

    Google Scholar 

  27. Toshiba America Electronic Components, Inc.: NAND flash applications design guide (2004)

    Google Scholar 

  28. Lee, S., Moon, B.: Design of flash-based DBMS: an in-page logging approach. In: Proceedings of ACM International Conference on Management of Data (2007)

    Google Scholar 

  29. Birrel, A., Isard, M., Thacker, C., Wobber, T.: A design for high-performance flash disks. Technical Report MSR-TR-2005-176, Microsoft Research (2005)

    Google Scholar 

  30. Park, S., D.Jung, Kang, J., Kim, J., Lee, J.: CFLRU: a replacement algorithm for flash memory. In: Proceedings of International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp. 234–241 (2006)

    Google Scholar 

  31. Samsung Electronics: datasheet K9G8G08UOM (2006)

    Google Scholar 

  32. Samsung Electronics: datasheet KPS1215EZM (2006)

    Google Scholar 

  33. Lam, C.: Cell design considerations for phase change memory as a universal memory. In: Proceedings of International Symposium on VLSI Technology, Systems and Applications, pp. 132–133 (2008). doi:10.1109/VTSA.2008.4530832

  34. Zhang, Y., et al.: An integrated phase change memory cell with Ge nanowire diode for cross-point memory. In: Proceedings of IEEE Symposium on VLSI Technology, pp. 98–99 (2007). doi:10.1109/VLSIT.2007.4339742

  35. Lee, K., et al.: A 90nm 1.8V 512Mb diode-switch PRAM with 266MB/s read throughput. In: Proceedings of IEEE International Solid-State Circuits Conference pp. 472–616 (2007). doi:10.1109/ISSCC.2007.373499

  36. Nirschl, T., et al.: Write strategies for 2 and 4-bit multi-level phase-change memory. In: Proceedings of IEEE International Electron Devices Meeting, pp. 461–464 (2007). doi:10.1109/IEDM.2007.4418973

  37. http://www.tpc.org

  38. Park, Y., Lim, S., Lee, C., Park, K.: PFFS: a scalable flash memory file system for the hybrid architecture of phase-change RAM and NAND flash. In: Proceedings of ACM Symposium on Applied Computing (2008)

    Google Scholar 

  39. Increasing flash solid state disk reliability. Technical Report, SiliconSystems (2005)

    Google Scholar 

  40. Chang, Y., Hsieh, J., Kuo, T.: Endurance enhancement of flash-memory storage systems: an efficient static wear leveling design. In: Proceedings of Design Automation Conference, pp. 212–217 (2007). doi:http://doi.acm.org/10.1145/1278480.1278533

  41. Jung, D., Chae, Y., Jo, H., Kim, J., Lee, J.: A group-based wear-leveling algorithm for large-capacity flash memory storage systems. In: Proceedings of International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp. 160–164 (2007). doi:http://doi.acm.org/10.1145/1289881.1289911

  42. http://hammerora.sourceforge.net/

  43. Shibata, N., et al.: A 70 nm 16GB 16-Level-Cell NAND flash memory. Proc. IEEE Symp. VLSI Circ. 43(4), 929–937 (2007). doi:10.1109/JSSC.2008.917559

    Google Scholar 

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Sun, G. (2014). Replacing Different Levels of the Memory Hierarchy with NVMs. In: Exploring Memory Hierarchy Design with Emerging Memory Technologies. Lecture Notes in Electrical Engineering, vol 267. Springer, Cham. https://doi.org/10.1007/978-3-319-00681-9_2

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  • DOI: https://doi.org/10.1007/978-3-319-00681-9_2

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