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Lateral Power Transistors with Trench Patterns

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Lateral Power Transistors in Integrated Circuits

Part of the book series: Power Systems ((POWSYS))

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Abstract

Another emerging technology which constitutes to progress beyond modern RESURF-based LDMOS transistors utilizes trench patterns. In this chapter the trench-based technology in LDMOS transistors is reviewed. First, the applicability of trench gates is motivated by a discussion on channel resistance. The impact of FinFET technology on lateral power transistors is investigated. To evaluate the feasibility of trench gates, device designs employing trench gates and their electrical properties under static and dynamic device operation are presented and discussed. Typical Figures-of-Merit obtained from these trench devices are compared to state-of-the-art LDMOS transistors. Considering the process technology, limitations for integration into smart-power ICs and RF amplifiers are also investigated.

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References

  1. D.J. Foster, in Electronic Materials, Silicon Processing: CMOS Technology (Springer, New York, 1991), pp. 173–191

    Google Scholar 

  2. D.J. Dumin, Oxide Reliability: A Summary of Silicon Oxide Wearout, Breakdown, and Reliability (World Scientific, Singapore, 2002)

    Google Scholar 

  3. S.C. Sun, J.D. Plummer, Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces. IEEE Trans. Electron Devices ED-27 (8), 1497–1508 (1980)

    Google Scholar 

  4. S. Takagi, A. Toriumi, M. Iwase, H. Tango, On the universality of inversion layer mobility in Si MOSFET’s: Part I-effects of substrate impurity concentration. IEEE Trans. Electron Devices 41(12), 2357–2362 (1994)

    Article  Google Scholar 

  5. R.S. Saxena, M.J. Kumar, in Trench Gate Power MOSFET: Recent Advances and Innovations, ed. by S. Jit. Advances in Microelectronics and Photonics (Nova Science Publishers Inc., New York, 2012), pp. 1–23

    Google Scholar 

  6. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, C. Hu, Sub 50-nm FinFET: PMOS, in International Electron Devices Meeting, Washington, USA, 1999

    Google Scholar 

  7. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, C. Hu, FinFET—A self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Devices 47(12), 2320–2325 (2000)

    Article  Google Scholar 

  8. B. Duan, Y. Yang, B. Zhang, X. Hong, Folded-accumulation LDMOST: new power MOS. IEEE Electron Device Lett. 30(12), 1329–1331 (2009)

    Article  Google Scholar 

  9. A. Nakagawa, Y. Kawaguchi, Improved 20 V lateral trench gate power MOSFETs with very low on-resistance of 7.8 mΩ mm2, in International Symposium on Power Semiconductor Devices and ICs, Toulouse, France, 2000

    Google Scholar 

  10. H. Wang, H.P.E. Xu, W.T. Ng, K. Fukumoto, K. Abe, A. Ishikawa, Y. Furukawa, H. Imai, T. Naito, N. Sato, K. Sakai, S. Tamura, K. Takasuka, A novel orthogonal gate EDMOS transistor with improved dv/dt capability and figure of merit (FOM). IEEE Electron Device Lett. 29(12), 1386–1388 (2008)

    Article  Google Scholar 

  11. M. Zitouni, F. Morancho, P. Rossel, H. Tranduc, J. Buxo, I. Pagès, A new concept for the lateral DMOS transistor for smart power IC’s, in International Symposium on Power Semiconductor Devices and ICs (ISPSD), Toronto, Canada, 1999

    Google Scholar 

  12. D. Disney, W. Chan, R. Lam, R. Blattner, S. Ma, W. Seng, J.-W. Chen, M. Cornell, R. Williams, 60 V lateral trench MOSFET in 0.35 µm technology, in International Symposium on Power Semiconductor Devices and ICs, Orlando, USA, 2008

    Google Scholar 

  13. I.-Y. Park, Y.-I. Choi, S.-K. Chung, H.-J. Lim, S.-I. Mo, J.-S. Choi, M.-K. Han, Numerical analysis on the LDMOS with a double epi-layer and trench electrodes. Microelectron. J. 32, 497–502 (2001)

    Article  Google Scholar 

  14. P. Moens, F. Bauwens, J. Baele, K. Vershinin, E. De Backer, E. M. Sankara Narayanan, M. Tack, XtreMOS: the first integrated power transistor breaking the silicon limit, in International Electron Device Meeting, San Francisco, USA, 2006

    Google Scholar 

  15. P. Moens, F. Bauwens, B. Desoete, J. Baele, K. Vershinin, H. Ziad, E. M. Shankara Narayanan und M. Tack, Record-low on-resistance for 0.35 µm based integrated XtreMOS transistors, in International Symposium on Power Semiconductor Devices and ICs, Jeju, Korea, 2007

    Google Scholar 

  16. T. Uesugi, M. Kodama, S. Kawaji, K. Nakashima, Y. Murase, E. Hayashi, Y. Mitsushima, H. Tadano, New 3-D lateral power MOSFETs with ultra low on-resistance, in International Symposium on Power Semiconductor Devices and ICs, Kyoto, Japan, 1998

    Google Scholar 

  17. N. Fujishima, A. Sugi, S. Kajiwara, K. Matsubara, Y. Nagayasu, C.A.T. Salama, A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact. IEEE Trans. Electron Devices 49(8), 1462–1468 (2002)

    Article  Google Scholar 

  18. T. Yan, H. Liao, Y.Z. Xiong, R. Zeng, J. Shi, R. Huang, Cost-effective integrated RF power transistor in 0.18-µm CMOS technology. IEEE Electron Device Lett. 27(10), 856–858 (2006)

    Article  Google Scholar 

  19. N. Fujishima, C.A.T. Salama, A trench lateral power MOSFET using self-aligned trench bottom contact holes, in International Electron Devices Meeting, Washington, USA, 1997

    Google Scholar 

  20. S.T. Peake, R. Grover, R. Farr, C. Rogers, G. Petkos, Fully self-aligned power trench-MOSFET utilising 1 µm pitch and 0.2 µm trench width, in International Symposium Power Semiconductor Devices and ICs, Santa Fe, USA, 2002

    Google Scholar 

  21. T. Erlbacher, A. J. Bauer, L. Frey, Significant on-resistance reduction of LDMOS devices by intermitted trench gates integration. IEEE Trans. Electron Devices 59, 3470–3476 (2012)

    Google Scholar 

  22. I. Cortes, P. Fernandez-Martinez, D. Flores, S. Hidalgo, J. Rebollo, Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates. Semicond. Sci. Technol. 23, 015009 (2008)

    Article  Google Scholar 

  23. P.H. Wilson, A novel trench gate LDMOS for RF applications, in International Crimean Conference on Microwave and Telecommunication Technology, Sevastopol, Ukraine, 2003

    Google Scholar 

  24. C.S. Kim, J.-W. Park H.K. Yu, Trenched sinker LDMOSFET (TS-LDMOS) structure for high power amplifier applications above 2 GHz, in International Electron Devices Meeting, Washington, USA, 2001

    Google Scholar 

  25. H. Xiao, L. Zhang, R. Huang, F. Song, D. Wu, H. Liao, W. Wong, Y. Wang, A novel RF LDMOS fabricated with standard foundry technology. IEEE Electron Device Lett. 30(4), 386–388 (2009)

    Article  Google Scholar 

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Authors and Affiliations

  1. Lehrstuhl für Elektronische Bauelemente, Universität Erlangen-Nürnberg, Erlangen, Germany

    Tobias Erlbacher

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  1. Tobias Erlbacher
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Correspondence to Tobias Erlbacher .

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© 2014 Springer International Publishing Switzerland

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Erlbacher, T. (2014). Lateral Power Transistors with Trench Patterns. In: Lateral Power Transistors in Integrated Circuits. Power Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-00500-3_7

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  • DOI: https://doi.org/10.1007/978-3-319-00500-3_7

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-00499-0

  • Online ISBN: 978-3-319-00500-3

  • eBook Packages: EnergyEnergy (R0)

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