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Lateral Power Transistors in Integrated Circuits pp 105–131Cite as

Lateral Power Transistors with Charge Compensation Patterns

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Part of the book series: Power Systems ((POWSYS))

Abstract

Among the promising candidates for future LDMOS devices is the charge compensated LDMOS transistor which is focused on in this chapter. Charge compensation patterns have been successfully introduced in vertical superjunction MOSFETs [1]. A transfer of this topology to lateral power MOSFETs appears intriguing due to the reduction of drift resistance further beyond the one-dimensional silicon limit. Using a unit cell for lateral power MOSFETs, the charge compensation patterns are presented and their operation principle is explained. Then, different device designs for LDMOS transistors employing these charge-compensated drift regions are presented. The evaluation of electrical properties for these charge compensated LDMOS transistors yields low static power losses and reduced switching losses. The feasibility of integration of charge compensation patterns into smart-power ICs is evaluated considering the process technology required for formation of these patterns.

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Authors and Affiliations

  1. Lehrstuhl für Elektronische Bauelemente, Universität Erlangen-Nürnberg, Erlangen, Germany

    Tobias Erlbacher

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  1. Tobias Erlbacher
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Correspondence to Tobias Erlbacher .

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© 2014 Springer International Publishing Switzerland

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Erlbacher, T. (2014). Lateral Power Transistors with Charge Compensation Patterns. In: Lateral Power Transistors in Integrated Circuits. Power Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-00500-3_6

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  • DOI: https://doi.org/10.1007/978-3-319-00500-3_6

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-00499-0

  • Online ISBN: 978-3-319-00500-3

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