Abstract
IGBT device destruction often occurs localized at the edge termination. Among various termination techniques, “variation of lateral doping” (VLD) is a promising candidate to increase the ruggedness of IGBT chips. We analyzed the time-dependent behavior of VLD edge termination during avalanche breakdown by numerical simulations demonstrating the advantage of this technique. Measurements on IGBT test devices with VLD edge termination are in agreement with the simulations.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
A. Icaza-Deckelmann, G. Wachutka, F. Hirler, J. Krumrey, R. Henninger, “Failure of multiple-cell power DMOS transistors in avalanche operation”, Proceedings of the 33rd European Solid-State Research Conference (ESSDERC) 2003, Estoril, Portugal, pp. 323–326.
DESSIS TCAD, distributed by Synopsis.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2007 Springer-Verlag Wien
About this paper
Cite this paper
Knipper, U., Pfirsch, F., Raker, T., Niedermeyr, J., Wachutka, G. (2007). Study of Time-Periodic Avalanche Breakdown Occurring in VLD Edge Termination Structures. In: Grasser, T., Selberherr, S. (eds) Simulation of Semiconductor Processes and Devices 2007. Springer, Vienna. https://doi.org/10.1007/978-3-211-72861-1_45
Download citation
DOI: https://doi.org/10.1007/978-3-211-72861-1_45
Publisher Name: Springer, Vienna
Print ISBN: 978-3-211-72860-4
Online ISBN: 978-3-211-72861-1
eBook Packages: EngineeringEngineering (R0)