Abstract
As the design rule is scaled down, the electrical isolation of metal lines becomes critical. In a high density flash memory with 37nm (pitch=74nm) technology, the threshold voltage shift of ∼0.3V is found to be caused by tungsten micro-bridge between adjacent bit-lines. Simulations and experimental data showed that tungsten re-sputtering is occurred during the deposition of HDP (High Density Plasma)-SiO2 used as the filling dielectric between tungsten bit-lines. In this paper, the model for the tungsten re-sputtering is presented. The plasma simulations are performed to investigate the effects of process factors of HDP-SiO2 deposition on the formation of micro-bridge using in-house tool, PIE simulator.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Kinam Kim et al., “Future Outlook of NAND Flash Technology for 40nm Node and Beyond”, IEEE NVSMW, pp. 9–11, 2006.
Jung-Dai Choi et al., “A 0.15 um NAND Flash Technology with 0.11 um2 Cell Size for 1 Gbit Flash Memory”, IEDM, pp. 767–770, 2000
Won-Young Chung et al., “Integrated Simulation of Equipment and Topography for Plasma Etching in the DRM Reactor”, SISPAD, pp. 127–130, 2000.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2007 Springer-Verlag Wien
About this paper
Cite this paper
Hwang, B. et al. (2007). Modeling of Re-Sputtering Induced Bridge of Tungsten Bit-Lines for NAND Flash Memory Cell with 37nm Node Technology. In: Grasser, T., Selberherr, S. (eds) Simulation of Semiconductor Processes and Devices 2007. Springer, Vienna. https://doi.org/10.1007/978-3-211-72861-1_11
Download citation
DOI: https://doi.org/10.1007/978-3-211-72861-1_11
Publisher Name: Springer, Vienna
Print ISBN: 978-3-211-72860-4
Online ISBN: 978-3-211-72861-1
eBook Packages: EngineeringEngineering (R0)