Abstract
The modeling of interconnect lines using lumped elements results in large nets that in general can only be handled after a reduction of these parasitic elements. This paper presents an alternative to the Padé via Lanczos methods like SymPVL which allows for a direct error estimation by working in the time domain instead of approximating the transfer function. The proposed method uses a direct eigenvalue calculation which is performed with the Jacobi Davidson algorithm.
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Reference
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© 2003 Springer Basel AG
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Kahlert, M. (2003). Parasitics Reduction for Analog Circuit Simulation. In: Antreich, K., Bulirsch, R., Gilg, A., Rentrop, P. (eds) Modeling, Simulation, and Optimization of Integrated Circuits. ISNM International Series of Numerical Mathematics, vol 146. Birkhäuser, Basel. https://doi.org/10.1007/978-3-0348-8065-7_14
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DOI: https://doi.org/10.1007/978-3-0348-8065-7_14
Publisher Name: Birkhäuser, Basel
Print ISBN: 978-3-0348-9426-5
Online ISBN: 978-3-0348-8065-7
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