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Examples: Leakage in DRAM Cell Structures

  • Roland Kircher
  • Wolfgang Bergner
Part of the Progress in Numerical Simulation for Microelectronics book series (PNSM)

Abstract

Dynamic random access memories (DRAMs) are devices where a large amount of information can be bit-wise stored by writing a certain amount of charge into a particular memory cell. A DRAM device contains a large number of these memory cells, which consist of only two separate device structures: the capacitor where the charge corresponding to the information is stored, and the switching transistor which controls the read and write access to the capacitor. This so-called one-transistor cell is characteristic for DRAMs. Because of its simple structure compared with static random access memories (SRAMs) or logic integrated circuits, the memory cell needs only a rather small area, and therefore, DRAMs have the advantage of high integration density. In addition, they provide a large number of identical structures with a relatively simple circuit environment to transfer the stored information to the outer world. These are the reasons why they are commonly used as test vehicles for a new technology generation. On the other hand, due to the restriction of the one-transistor cell the charge in the capacitor has to be refreshed after a certain time interval, the so-called refresh cycle time. This is neccessary because the charged capacitor is floating, i.e. disconnected from the switching or transfer transistor, and some amount of the charge is lost by generation-recombination processes in space charge regions. The refresh cycle time is in the order of 10 to about 100ms. If additional leakage mechanisms are present the resulting charge loss during one refresh cycle may become a serious problem. In the following, the most important leakage mechanisms which can affect the function of the DRAM cell are briefly introduced. Then we will focus on the investigation of one particular leakage mechanism as an illustration for the application of three-dimensional device simulation, and show how simulation can be used to improve and optimize the DRAM cell design. All examples have been investigated by utilizing the three-dimensional device simulator SITAR, which has been developed as a research tool to investigate trench-type device structures in DRAM memory cells, and to optimize efficiently technological parameters for the process engineers engaged in the development of VLSI and ULSI devices. Although SITAR has originally been designed for trench cells, it is steadily developed towards a three-dimensional device simulator for arbitrary device structures. The examples presented in this chapter give only a slight impression on the features and possible applications of this simulator.

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Copyright information

© Springer Basel AG 1991

Authors and Affiliations

  • Roland Kircher
    • 1
  • Wolfgang Bergner
    • 1
  1. 1.ZFE SPTSiemens AGMünchen 83Germany

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