Within the last two decades, device simulation became an important tool for investigating the potential distribution and the carrier transport in semiconductor structures. The very first simulation programs solved Poisson’s equation and one carrier continuity equation in steady state and on a one-dimensional spatial grid, and with rather simple numerical methods and approximations, due to the limited computer resources at that time. With increasing speed and memory of the computers, the simulation programs could be extended into two dimensions, leading to a more realistic description of the geometry and the structure of the devices. The standard numerical methods have been improved, and new sophisticated algorithms have been developed, reducing the computational effort in the simulation. In addition, much effort has been spent to leave the crude approximations for the carrier transport and to develop more accurate physical models, taking into account all important physical effects in the devices. This triggered a dramatic innovation in the semiconductor technology, resulting in a tremendous miniaturization of the device structures, which had again and still has, a significant impact on the development of the simulation tools. Furthermore, due to these rapid innovation cycles, the development and fabrication of such small devices has become very expensive and time-consuming. The simulation can drastically reduce the learning cycles, needed for the development of new device structures and their processes, by predicting the electrical behavior of the structure, thus reducing costs and time. The present state of integration density would be impossible without the support of the various simulation tools. About one decade ago already, the two-dimensional device simulation proved to be an important and necessary engineering tool for the development of bipolar, MOS and other VLSI structures, and for the optimization of their geometry, the doping distribution and electrical characteristics.
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