Abstract
Java Bytecode is used as binary format for a number of programming languages and programming systems. Since Java virtual machines exist for many platforms, it can be regarded as a universal execution format. Consequently, several hardware implementations of Bytecode processors exist. Unfortunately, they all suffer from the inefficiencies of the Bytecode principle. Particularly, the operand stack and the local variable storage are bottlenecks during execution. In this contribution, we evaluate the performance gain that can be achieved by replacing Bytecode with a data flow oriented instruction set architecture (ISA). We describe the changes that are necessary to adapt an existing Bytecode processor to the new ISA. Ultimately, we compare execution times and HW resources for both processors, which are based on identical ALUs and heap memory model. Execution times are evaluated using the SPEC JVM98 benchmark and a set of micro benchmarks which have a very flat call graph. SPEC JVM98 reaches a speedup of 1.76 and the micro benchmarks even gain a factor of 2.80.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
aJile Systems: Real-time, Low Power Network, Multimedia Direct Execution Microprocessor For The JME Platform aJ-200. Technical Reference Manual (2010)
Dennis, T.: Data flow supercomputers. Computer 13(11), 48–56 (1980)
Gatzka, S., Hochberger, C.: The AMIDAR class of reconfigurable processors. J. Supercomput. 32(2), 163–181 (2005)
Gruian, F., Westmijze, M.: Investigating hardware micro-instruction folding in a Java embedded processor. In: JTRES 2010, pp. 102–108. ACM, New York, August 2010
Gurd, J.R., Kirkham, C.C., Watson, I.: The Manchester prototype dataflow computer. Commun. ACM 28(1), 34–52 (1985)
Hochberger, C., Jung, L.J., Engel, A., Koch, A.: Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processors. In: DASIP 2021, pp. 1–6, October 2014 (2014)
Lee, B., Hurson, A.R.: Issues in dataflow computing. In: Advances in Computers, vol. 37, pp. 285–333. Elsevier, January 1993
Schoeberl, M.: A Java processor architecture for embedded real-time systems. J. Syst. Archit. 54(1), 265–286 (2008)
Schwarz, A., Hochberger, C.: Engineering an optimized instruction set architecture for AMIDAR processors. In: Brinkmann, A., et al. (eds.) ARCS 2020. LNCS, vol. 12155, pp. 124–137. Springer, Cham (2020). https://doi.org/10.1007/978-3-030-52794-5_10
Standard Performance Evaluation Corporation: SPEC JVM98 Benchmarks. https://www.spec.org/jvm98/, Accessed 24 Mar 2021
Sun Microsystems: picoJava-II Microarchitecture Guide. Technical Report (1999)
Sun Microsystems: picoJava-II Programmer’s Reference Manual. Technical Report (1999)
Ton, L.R., Chang, L.C., Shann, J.J., Chung, C.P.: Design of an optimal folding mechanism for Java processors. Microprocess. Microsyst. 26(8), 341–352 (2002)
Tsai, C., Lin, C., Chen, C., Lin, Y., Ji, W., Hong, S.: Hardwiring the OS kernel into a Java application processor. In: ASAP, pp. 53–60 (2017)
Uhrig, S., Wiese, J.: jamuth: an IP processor core for embedded Java real-time systems. In: JTRES 2007, pp. 230–237. ACM, New York, September 2007
Wolf, D.L., Jung, L.J., Ruschke, T., Li, C., Hochberger, C.: AMIDAR Project: lessons learned in 15 years of researching adaptive processors. In: ReCoSoC 2018, pp. 1–8, July 2018
Yiyu, T., Fong, A.S., Xiaojian, Y.: An instruction folding solution to a java processor. In: Li, K., Jesshope, C., Jin, H., Gaudiot, J.-L. (eds.) NPC 2007. LNCS, vol. 4672, pp. 415–424. Springer, Heidelberg (2007). https://doi.org/10.1007/978-3-540-74784-0_42
Zabel, M., Spallek, R.G.: Application requirements and efficiency of embedded Java bytecode multi-cores. In: JTRES 2010, pp. 46–52. ACM, New York, August 2010
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2021 Springer Nature Switzerland AG
About this paper
Cite this paper
Schwarz, A., Hochberger, C. (2021). Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode. In: Hochberger, C., Bauer, L., Pionteck, T. (eds) Architecture of Computing Systems. ARCS 2021. Lecture Notes in Computer Science(), vol 12800. Springer, Cham. https://doi.org/10.1007/978-3-030-81682-7_7
Download citation
DOI: https://doi.org/10.1007/978-3-030-81682-7_7
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-81681-0
Online ISBN: 978-3-030-81682-7
eBook Packages: Computer ScienceComputer Science (R0)