Detecting Uncertain BNN Outputs on FPGA Using Monte Carlo Dropout Sampling

Abstract

Monte Carlo dropout sampling (MC Dropout), which approximates a Bayesian Neural Network, is useful for measuring the uncertainty in the output of a Deep Neural Network (DNN). However, because it takes a long time to sample DNN’s output for calculating its distribution, it is difficult to apply it to edge computing where resources are limited. Thus, this research proposes a method of reducing a sampling time required for MC Dropout in edge computing by parallelizing the calculation circuit using FPGA. To apply MC dropout in an FPGA, this paper shows an efficient implementation by binarizing the neural network and simplifying dropout computation by pre-dropout and localizing parallel circuits. The proposed method was evaluated using the MNIST dataset and a dataset of satellite images of ships at sea captured. As a result, it was possible to reject approximately 60% of data which the model had not learned as “uncertain” on a classification identification problem of the image on an FPGA. Furthermore, for 20 units in parallel, the amount of increase in the circuit scale was only 2–3 times that of non-parallelized circuits. In terms of inference speed, parallelization of dropout circuits has achieved up to 3.62 times faster.