Abstract
The Three-Independent-Gate Field-Effect Transistor (TIGFET) is a promising beyond-CMOS technology which offers multiple modes of operation enabling unique capabilities such as the dynamic control of the device polarity and dual-threshold voltage characteristics. These operations can be used to reduce the number of transistors required for logic implementation resulting in compact logic designs and reductions in chip area and leakage current.
However, the evaluation of TIGFET-based design currently relies on a close approximation for the Power, Performance, and Area (PPA) rather than traditional layout-based methods. To allow for a systematic evaluation of the design area, we present here a publicly available Predictive Process Design Kit (PDK) for a 10 nm-diameter silicon-nanowire TIGFET device. This work consists of a SPICE model and full custom physical design files including a Design Rule Manual, a Design Rule Check, and Layout Versus Schematic decks for Calibre®. We validate the design rules through the implementation of basic logic gates and a full-adder and compare extracted metrics with the FreePDK15nmTM PDK. We show 26% and 41% area reduction in the case of an XOR gate and a 1-bit full-adder design respectively. Applications for this PDK with respect to hardware security benefits are supported through a differential power analysis study.
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Acknowledgements
This work was supported by the NSF Career Award number 1751064, and the SRC Contract 2018-IN-2834.
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Cadareanu, P., Gore, G., Giacomin, E., Gaillardon, PE. (2020). A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. In: Metzler, C., Gaillardon, PE., De Micheli, G., Silva-Cardenas, C., Reis, R. (eds) VLSI-SoC: New Technology Enabler. VLSI-SoC 2019. IFIP Advances in Information and Communication Technology, vol 586. Springer, Cham. https://doi.org/10.1007/978-3-030-53273-4_14
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