Abstract
Multi-Processor System-on-Chips (MPSoCs) is a standard platform used in time-critical applications. These platforms usually employ Priority-Preemptive NoCs (PP-NoCs), a widely used real-time on-chip interconnection structure that offers communication predictability. A deep analysis of the PP-NoC parameters and their impact on system security is required. Moreover, countermeasures that can protect the system while guaranteeing the real-time capabilities should be proposed and evaluated. To this end, this paper explores and evaluates the impact of the PP-NoCs parameters on system security; exploits PP-NoCs vulnerabilities and demonstrates for the first time two very powerful attacks; and proposes and integrates three new security countermeasures: RT-blinding, RT-masking, and RT-shielding. Results show that PP-NoCs are vulnerable to attacks and that is possible to uncover victim’s information with high accuracy (up to 96.19%). On the other hand, protection techniques were able to harden the system, effectively and efficiently mitigating the vulnerabilities while maintaining deterministic behavior.
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Notes
- 1.
Following the classical cache attack, Prime+Probe from Osvik et al. [18], the best moment to probe a cache is when all the accesses to the cache depends only on the value of the secret key used for encryption.
References
Sapra, D., Altmeyer, S.: Work-in-progress: design-space exploration of multi-core processors for safety-critical real-time systems. In: 2017 IEEE RTSS, pp. 360–362 (December 2017)
Rockwood, M., Joshi, V., Sullivan, K., Goubran, R.: Using a real-time operating system for multitasking in remote patient monitoring. In: 2014 IEEE MeMeA, pp. 1–5 (June 2014)
Bolotin, E., Cidon, I., Ginosar, R., Kolodny, A.: Qnoc: Qos architecture and design process for network on chip. J. Syst. Archit. 50, 105–128 (2004)
Lo, S., Lan, Y., Yeh, H., Tsai, W., Hu, Y., Chen, S.: Qos aware binoc architecture. In: 2010 IEEE IPDPS, pp. 1–10 (April 2010)
Nikolić, B., Petters, S.M.: EDF as an arbitration policy for wormhole-switched priority-preemptive NOCs - myth or fact? In: 2014 EMSOFT, pp. 1–10 (October 2014)
Shi, Z., Burns, A.: Real-time communication analysis for on-chip networks with wormhole switching. In: Second ACM/IEEE International Symposium on Networks-on-Chip (NOCs 2008), pp. 161–170 (April 2008)
Indrusiak, L.S., Burns, A., Nikolić, B.: Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NOCs. In: 2018 DATE, pp. 219–224 (March 2018)
Yao, W., Suh, E.: Efficient timing channel protection for on-chip networks. In: NOCS 2012 Proceedings of the 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, Lyngby, Denmark, pp. 142–151. IEEE (May 2012)
Daoud, L., Rafla, N.: Analysis of black hole router attack in network-on-chip. In: 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 69–72 (August 2019)
Sepúlveda, J., Diguet, J.P., Strum, M., Gogniat, G.: NoC-based protection for SoC time-driven attacks. IEEE Embed. Syst. Lett. 7(1), 7–10 (2015)
Reinbrecht, C., Forlin, B., Zankl, A., Sepúlveda, J.: Earthquake - a NoC-based optimized differential cache-collision attack for MPSoCs. In: 2018 DATE, Dresden, Germany, pp. 1–7. ACM (March 2018)
Reinbrecht, C., Susin, A., Bossuet, L., Sepulveda, J.: Gossip NoC - avoiding timing side-channel attacks through traffic management. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016), Pittsburgh, USA, pp. 601–606. IEEE (July 2016)
Sepúlveda, J., Gross, M., Zankl, A., Sigl, G.: Exploiting bus communication to improve cache attacks on systems-on-chips. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017) (July 2017)
Forlin, B., Reinbrecht, C., Sepúlveda, J.: Attacking real-time MPSoCs: preemptive NoCs are vulnerable. In: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), pp. 204–209 (October 2019)
Stefan, R., Goossens, K.: Enhancing the security of time-division-multiplexing networks-on-chip through the use of multipath routing (2011)
Chaves, C.G., Azad, S.P., Hollstein, T., Sepulveda, J.: A distributed dos detection scheme for NoC-based MPSoCs. In: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), pp. 1–6 (October 2018)
Reinbrecht, C., Susin, A., Bossuet, L., Sigl, G., Sepulveda, J.: Side channel attack on NoC-based MPSoCs are practical: NoC prime+probe attack. In: 29th Symposium on Integrated Circuits and Systems Design (SBCCI), Belo Horizonte, Brazil, pp. 1–6. IEEE (August 2016)
Osvik, D.A., Shamir, A., Tromer, E.: Cache attacks and countermeasures: the case of AES. In: Pointcheval, D. (ed.) CT-RSA 2006. LNCS, vol. 3860, pp. 1–20. Springer, Heidelberg (2006). https://doi.org/10.1007/11605805_1
Indrusiak, L.S., Harbin, J.R., Reinbrecht, C., Sepúlveda, M.J.: Side-channel protected MPSoC through secure real-time networks-on-chip. Microprocess. Microsyst. 68, 34–46 (2019)
Yao, W., Suh, E.: Efficient timing channel protection for on-chip networks. In: 2012 Sixth IEEE/ACM International Symposium on Networks on Chip (NoCS), pp. 142–151 (2012)
Wassel, H., et al.: Networks on chip with provable security properties. IEEE Micro 34(3), 57–68 (2014)
Sepulveda, J., Florez, D., Soeken, M., Diguet, J., Gogniat, G.: Dynamic NoC buffer allocation for MPSoC timing side channel attack protection. In: Network-on-Chip, Timing, Side Channel Attack (LASCAS), Florianópolis, Brazil, pp. 91–94. IEEE (March 2016)
Traber, A., Stucki, S., Zaruba, F., Gautschi, M., Pullini, A., Benini, L.: Pulpino: a RISC-V based single-core system. In: ORCONF2015, October 9–11, 2015, Geneva, Switzerland (2015)
Xiong, Q., Wu, F., Lu, Z., Xie, C.: Extending real-time analysis for wormhole NoCs. IEEE Trans. Comput. 66(9), 1532–1546 (2017)
Reinbrecht, C., Susin, A., Bossuet, L., Sigl, G., Sepúlveda, J.: Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection. Microprocess. Microsyst. 51, 556–565 (2017)
Reinbrecht, C., Forlin, B., Sepúlveda, J.: Cache timing attacks on NoC-based MPSoCs. Microprocess. Microsyst. 66, 1–9 (2019)
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Forlin, B., Reinbrecht, C., Sepúlveda, J. (2020). Security Aspects of Real-Time MPSoCs: The Flaws and Opportunities of Preemptive NoCs. In: Metzler, C., Gaillardon, PE., De Micheli, G., Silva-Cardenas, C., Reis, R. (eds) VLSI-SoC: New Technology Enabler. VLSI-SoC 2019. IFIP Advances in Information and Communication Technology, vol 586. Springer, Cham. https://doi.org/10.1007/978-3-030-53273-4_10
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