Abstract
This section is essentially a systematized review of the results of studies dedicated to methods of counteracting hardware Trojans in microcircuits . It should be said from the very beginning that there are no such countermeasures that would ensure absolute protection from such threats. As noted above, there are no methods that would allow 100% identification of defects in manufactured microcircuits.
Wide variety of hardware Trojans creates equally wide variety of associated security threats, which has lead to the necessity to develop concepts of ensuring secure operation of systems containing infected microcircuits.
One of the ways to solve this task is the prevention of the possibility of activation of introduced Trojans. Security can be improved with the help of multi-level protection, in which every level is independently aimed at certain mechanisms of Trojan activation with subsequent integration of all these measures into general strategy of system protection.
Today, hundreds of research teams all around the world are looking for effective ways to solve this task.
At first, we will present an overview of the most common methods of hardware and software protection—data protection, protected microcircuit architectures on the RTL level, reconfigurable microcircuit architectures, replication, and other protection methods.
After that, we will consider the architectural solutions of a Trojan-resistant system on chip, features of applying the IEEE 1500 standard, using mathematical instruments of the games theory, classic methods of information forensic and features of using a sandbox to protect SoC from Trojans . We will also separately consider the method of FPGA protection from unauthorized copying based on the Identification Friend or Foe method.
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E. Kuznetsov, A. Saurov, Hardware trojans. Part 4: software and hardware countermeasures. Nanoindustry 2, 42 (2017)
E. Kuznetsov, A. Saurov, Hardware trojans. Part 1: new threats to cyber security. Nanoindustry 7(69), 16–25 (2016)
E. Kuznetsov, A. Saurov, Hardware trojans. Part 3: examples of implementation, means of introduction and activation. Nanoindustry 8(70), 12–21 (2016)
A. Waksman, S. Sethumadhavan, Silencing hardware backdoors. Security and Privacy (SP), 2011 IEEE Symposium. IEEE, 49–63 (2011)
C. Gentry, Computing arbitrary functions of encrypted data. Communications of the ACM 53(3), 97–105 (2010)
R.S. Chakraborty, S. Narasimhan, S. Bhunia, Hardware trojan: threats and emerging solutions, in High Level Design Validation and Test Workshop, 2009. HLDVT 2009. IEEE International. IEEE (2009), 166–171
LW. Kim, J.D. Villasenor, C.K. Koc, A trojan-resistant system-on-chip bus architecture, in Military Communications Conference, 2009. MIL-COM 2009. IEEE (2009), pp. 1–6
A. Das et al., Detecting/preventing information leakage on the memory bus due to malicious hardware, in Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association (2010), pp. 861–866
G. Bloom et al., Providing secure execution environments with a last line of defense against trojan circuit attacks. Comput. Sec. 28(7), 660–669 (2009)
G.E. Suh et al., AEGIS: architecture for tamper-evident and tamper-resistant processing, in Proceedings of the 17th annual international conference on Supercomputing. ACM (2003), pp. 160–171
M. Anderson, C. North, K. Yiu, Towards countering the rise of the silicon trojan. DSTO Technical Report DSTOTR-2220. DSTO Information Sciences Laboratory (2008)
M. Hicks et al., Overcoming an untrusted computing base: detecting and removing malicious hardware automatically, in Security and Privacy (SP), 2010 IEEE Symposium. IEEE (2010), pp. 159–172
A. Belous, V. Saladukha, S. Shvedau, in Space Microelectronics, vol. 1, 2 (Artech House, London, 2017). ISBN: 9781630812577
C. Sturton et al., Defeating UCI: building stealthy and malicious hardware, in Security and Privacy (SP), 2011 IEEE Symposium. IEEE (2011), pp. 64–77
M. Abramovici, P. Bradley, Integrated circuit w security: new threats and solutions, in Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies. ACM, p. 55
D.Y. Deng, A.H. Chan, G.E. Suh, Hardware authentication leveraging performance limits in detailed simulations and emulations, in Proceedings of the 46th Annual Design Automation Conference. ACM (2009) 682–687
J.B. Webb, Methods for securing the integrity of FPGA configurations. Dis. Virginia Polytechnic Institute and State University (2006)
S. Trimberger, Trusted design in FPGAs, in Design Automation Conference, 2007. DAC’07. 44th ACM/IEEE. IEEE (2007), pp. 5–8
A. Baumgarten, A. Tyagi, J. Zambreno, Preventing IC piracy using reconfigurable logic barriers. IEEE Des. Test Comput. 27(1), 66–75 (2010)
T. Huffmire et al., Moats and drawbridges: an isolation primitive for reconfigurable hardware based systems, in Security and Privacy, 2007. SP’07. IEEE Symposium. IEEE (2007), pp. 81–295
M.L. Silva, J.C. Ferreira, Creation of partial FPGA configurations at run-time, in Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference. IEEE (2010), pp. 80–87
B. Newgard, C. Hoffman, Using multiple processors in a single reconfigurable fabric for high-assurance applications, in Hardware-Oriented Security and Trust (HOST), 2010 IEEE International Symposium on. IEEE (2010), pp. 25–29
D. McIntyre et al., Dynamic evaluation of hardware trust, in Hardware-Oriented Security and Trust, 2009. HOST 09. IEEE International Workshop. IEEE (2009), pp. 108–111
S.S. Kumar et al., The butterfly PUF protecting IP on every FPGA, in Hardware-Oriented Security and Trust, 2008. HOST 2008. IEEE International Workshop. IEEE (2008) pp. 67–70
G. Trouessin et al., Improvement of data processing security by means of fault tolerance, in Proceedings Of The 14th National Computer Security Conference (NCSC’14) (1991.), pp. 295–304
A. Shamir, How to share a secret. Commun. ACM 22 (11), 612–613 (1979)
E. Kuznetsov, A. Saurov, Hardware trojans. Part 2: prevention and detection methods. Nanoindustry 1(71), 30–40 (2017)
K. Jarvinen et al., Garbled circuits for leakage-resilience: hardware implementation and evaluation of one-time programs, in Cryptographic Hardware and Embedded Systems, CHES 2010, (Springer Berlin Heidelberg, 2010), pp. 383–397
L.-W. Kim, J.D. Villasenor, C.K. Koc, A trojan-resistant system-on-chip bus architecture. Electrical Engineering Department, University of California, Los Angeles 2 Computer Science Department, University of California, Santa Babara May 15 (2009)
F. Wolff, C. Papachristou, S. Bhunia, R. Chakraborty, Towards trojan-free trusted ICs: problem analysis and detection scheme, in Proceedings, Design Automation and Test in Europe (DATE’09) (Munich, Germany, March 10—14, 2008), pp. 1362—1365
Y. Jin, Y. Makris, Hardware trojan detection using path delay fingerprint, in IEEE International Workshop on Hardware-Oriented Security and Trust (HOST’08) (2008), pp. 51–57
X. Wang. Hardware trojan attacks: threat analysis and low-cost countermeasures through golden-free detection and secure design, January (2014)
DARPA. TRUST, in Integrated Circuits (TIC) (2007). http://www.darpa.mil/MTO/solicitations/baa07-24
R.S. Chakraborty, S. Narasimhan, S. Bhunia, Hardware trojan: threats and emerging solutions, in High-Level Design Verification and Test Workshop (2009)
L. Lin, W. Burleson, C. Parr, MOLES: malicious o_-chip leakage enabled by side- channels. Int. Conf. Comput.-Aided Des (2009)
Y. Jin, Y. Makris, Hardware trojans in wireless cryptographic ICs. IEEE Des. Test Comput. 27(1), 26–35 (2010)
Cyber Security Awareness Week ESC. http://www.poly.edu/csaw-embedded
X. Wang, S. Narasimhan, A. Krishna, T. Mal-Sarkar, S. Bhunia, Sequential hardware trojan: side-channel aware design and placement, in IEEE 29th International Conference on Computer Design (ICCD) (2011)
A. Maiti, J. Casarona, L. McHale, P. Schaumont, A large scale characterization of RO-PUF, in Proc. IEEE Intl. Workshop on Hardware-Oriented Security and Trust (HOST) (2010)
S. Narasimhan, X. Wang, D. Du, R.S. Chakraborty, S. Bhunia, TeSR: a robust temporal self-referencing approach for hardware trojan detection, in Proc. IEEE Intl. Workshop on Hardware-Oriented Security and Trust (HOST) (2011)
X. Wang, T. Mal-Sarkar, A. Krishna, S. Narasimhan, S. Bhunia, Software exploitable hardware trojans in embedded processor, in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2012)
M. Tehranipoor, F. Koushanfar, A survey of hardware Trojan taxonomy and detection. IEEE Des. Test Comput. 27(1), 10–25 (2010)
Y Jin, Y. Makris. Hardware trojan detection using path delay finngerprint, HOST (2008)
S.T. King et al., Designing and implementing malicious hardware, in USENIX Workshop on LEET (2008)
R.R. Rivest, The RC5 Encryption Algorithm, FSE (1994)
R. Karri, J. Rajendran, K. Rosenfeld, M. Tehranipoor. Toward trusted hardware: Identifying and classifying hardware Trojans. IEEE Computer Magazine (2010)
A.R. Alameldeen, D.A. Wood, in Adaptive Cache Compression for High Performance Processors. ISCA (2004)
H. Asadi et al., in Reliability Tradeoffs in Design of Cache Memories. Workshop on Architectural Reliability (2005)
A.J. van de Goor, Using March Tests to Test SRAMs. IEEE Des. Test Comput. March (1993)
S. Hamdioui, A.J. van de Goor, An Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests. ATS (2000)
S. Hamdioui et al., in Memory Test Experiment: Indistrial Results and Data, IEE Proceedings (2006)
Predictive Technology Model. http://www.eas.asu.edu/_ptm/
Y. Lu et al., FPGA implementation and analysis of random delay insertion countermeasure against DPA, in Proceedings of the International Conference on ICECE Technology (FTP08) (2008)
D. Hely et al., Scan design and secure chip, in IEEE Intl. On-Line Testing Symposium (2004)
Synopsys Veri_cation IP: http://www.synopsys.com/Tools/Verification/FunctionalVeri_cation/Veri_cationIP/Pages/default.aspx
P. Bernardi et al., Exploiting an I-IP for in-_eld SoC test. DFT (2004)
S. Narasimhan et al., Improving IC security against trojan attacks through integration of security monitors. IEEE Des. Test Comput. Spec. Iss. Smart Sili. (2012)
Intellitech Test-IP Product Family: http://www.intellitech.com/-products/boundaryscantest.asp
S. Tabatabaei et al., Embedded timing analysis: a SoC infrastructure. IEEE Des. Test Comput. (2002)
E. Dupont et al., Embedded robustness IPs for transient-error-free ICs. IEEE Des. Test Comput. (2002)
J. Bordelon et al., A strategy for mixed-signal yield improvement. IEEE Des. Test Comput. (2002)
Y. Zorian., Guest editor’s introduction: what is infrastructure IP? IEEE Des. Test Comput (2002)
F. DaSilva et al., Overview of the IEEE P1500 standard. ITC (2003)
IEEE 1500 Embedded Core Test: http://grouper.ieee.org/groups/1500/
IEEE 1450.6 Core Test Language (CTL): http://grouper.ieee.org/groups/ctl/
D.D. Josephson et al., Debug methodology for the McKinley processor. ITC (2001)
B. Yang et al., Secure scan: a design-for-test architecture for crypto chips. DAC (2005)
J. Lee et al., Securing scan design using lock & key technique. DFT (2005)
S. Paul et al., VIm-scan: a low overhead scan design approach for protection of secret key in scan-based secure chips. VTS (2007)
Q. Xu et al., Delay fault testing of core-based systems-on-a-chip. Date (2003)
X. Wang et al., Role of power grid in side channel attack and power-grid-aware secure design. DAC (2013)
Towards a Hardware Trojan Detection Cycle, Adrian Dabrowski, Heidelinde Hobel, Johanna Ullrich, Katharina Krombholz, Edgar Weippl SBA Research, Vienna, Austria, E-mail: (firstletterfirstname) (lastname)@sba-research.org
X. Wang, S. Narasimhan, A.R. Krishna, T. Mal-Sarkar, S. Bhunia, Sequential hardware trojan: Side-channel aware design and placement, in 2011 IEEE 29th International Conference on Computer Design (ICCD) (2011), pp. 297—300
H. Khattri, N.K.V Mangipudi, S. Mandujano, Hsdl: a security development lifecycle for hardware technologies, in Hardware-Oriented Security and Trust (HOST), 2012 IEEE International Symposium on. IEEE (2012), pp. 116—121
O.C. Gotel, C. Finkelstein. An analysis of the requirements traceability problem, in Requirements Engineering, 1994. Proceedings of the First International Conference on. IEEE (1994), pp. 94–101
C. Krieg, A. Dabrowski, H. Hobel, K. Krombholz, E. Weippl. Hardware malware. Synt. Lect. Inf. Sec. Pri. Trust 4(2), 1–115 (2013)
A. Dabrowski, P. Fejes, J. Ullrich, K. Krombholz, H. Hobel, E. Weippl, Poster: hardware trojans—detect and react? in Network and Distributed System Security (NDSS) Symposium, 2014, Extended Abstract and Poster Session. Internet Society (2014)
G. Becker, F. Regazzoni, C. Paar, W Burleson, Stealthy dopantlevel hardware trojans, in Cryptographic Hardware and Embedded Systems—CHES 2013, ser. Lecture Notes in Computer Science, vol. 8086, G. Bertoni, J.-S. Coron (eds.) (Springer Berlin, Heidelberg, 2013), pp. 197–214
M. Rathmair, F. Schupfer, Hardware trojan detection by specifying malicious circuit properties, in Proceedings of 2013 IEEE 4th International Conference on Electronics Information and Emergency Communication (2013), pp. 394—397
S. Smith, J. Di, Detecting malicious logic through structural checking, in IEEE Region 5 2007: Proceedings of the Region 5 Technical Conference (2007), pp. 217—222
X. Zhang, M. Tehranipoor, Case study: detecting hardware trojans in third-party digital IP cores, in HOST 2011: Proceedings of the IEEE Hardware-Oriented Security and Trust Symposium (2011), pp. 67—70
R.S. Chakraborty, S. Bhunia, Security against hardware trojan through a novel application of design obfuscation, in ICCAD 2009: Proceedings of the International Conference on Computer-Aided Design (2009), pp. 113—116
M. Banga, M. Hsiao, A region based approach for the identification of hardware trojans, in HOST 2008: Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust (2008)
C. Lamech, R. Rad, M. Tehrani, J. Plusquellic, An experimental analysis of power and delay signal-to-noise requirements for detecting trojans and methods for achieving the required detection sensitivities. IEEE Trans. Inf. Forensics Sec. 6, 1170–1179 (2011)
X. Zhang, N. Tuzzio, M. Tehranipoor, Red team: design of intelligent hardware trojans with known defense schemes, in 2011 IEEE 29th International Conference on Computer Design (ICCD) (2011), pp. 309–312
F. Koushanfar, A. Mirhoseini, A unified framework for multimodal submodular integrated circuits trojan detection. IEEE Trans. Inf. Forensics Sec. 6, 162–174 (2011)
H. Salmani, M. Tehranipoor, J. Plusquellic, A novel technique for improving hardware trojan detection and reducing trojan activation time, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2011)
M. Banga, M. Hsiao, A novel sustained vector technique for the detection of hardware trojans, in VLSI Design 2009: 22nd International Conference on VLSI Design (2009), pp. 327–332
S. Wei, S. Meguerdichian, M. Potkonjak, Gate-level characterization: foundations and hardware security applications, in DAC 2010: Proceedings of the 47th Conference on Design Automation (2010), pp. 222–227
C. Bobda, J. Mead, T.J-L. Whitaker, C. Kamhoua, K. Kwiat, Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on Chip. University of Arkansas JBHT Building Fayetteville, AR 72701, Air Force Research Lab Cyber Assurance Branch 525 Brooks Road Rome, NY 13441 charles.kamhoua.1@us.af.mil, kevin
S. Bhunia, M. Hsiao, M. Banga, S. Narasimhan, Hardware trojan attacks: threat analysis and countermeasures. Proce. IEEE 102(8), pp. 1229—1247, August (2014)
M. Tehranipoor, F. Koushanfar, A survey of hardware trojan taxonomy and detection. Des. Test Comput. IEEE. 27(1), 10–25 January (2010)
S. Mitra, H.S.P. Wong, S. Wong, Stopping hardware trojans in their tracks. A few adjustments could protect chips against malicious circuitry January (2015). http://spectrum.ieee.org/semiconductors/design/stopping-hardware-trojansin-their-tracks
Y. Alkabani, F. Koushanfar, M. Potkonjak, Remote activation of ICs for piracy prevention and digital right management, in ICCAD (2007), pp. 674—677
IEEE standard for property specification language (psl). IEEE Std 1850–2010 (Revision of IEEE Std 1850-2005), April (2010), pp. 1-18
R.S. Chakraborty, S. Bhunia, Security against hardware trojan attacks using key-based design obfuscation. J. Elect. Test. 27(6), 767–785 (2011). https://doi.org/10.1007/s10836-011-5255-2
Y. Alkabani, F. Koushanfar, Active hardware metering for intellectual property protection and security, in USENIX Security Symp (2007), pp. 291—306
M. Banga, M. Hsiao, A region based approach for the identification of hardware trojans, in Hardware-Oriented Security and Trust, 2008. HOST 2008. IEEE International Workshop, June (2008), pp. 40–47
D. Forte, C. Bao, A. Srivastava, Temperature tracking: an innovative run-time approach for hardware trojan detection, in Computer-Aided Design (ICCAD), 2013 IEEE/ACM International Conference, November (2013), pp. 532–539
C. Lamech, R. Rad, M. Tehranipoor, J. Plusquellic, An experimental analysis of power and delay signal-to-noise requirements for detecting trojans and methods for achieving the required detection sensitivities. Inf. Forensics Sec. IEEE Trans. 6(3), 1170–1179 September (2011)
B. Cakir B, S. Malik, Hardware trojan detection for gate-level ics using signal correlation based clustering, Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition. DATE’15 (EDA Consortium, San Jose, CA, USA 2015), 471–476. http://dl.acm.org/citation.cfm?id=2755753.2755860
A. Sengupta, S. Bhadauria, Untrusted third party digital ip cores: Power-delay trade-off driven exploration of hardware trojan secured data path during high level synthesis, in Proceedings of the 25th Edition on Great Lakes Symposium on VLSI. Р 167–172. GLSVLSI’15 (ACM, New York, NY, USA, 2015). http://doi.acm.org/10.1145/2742060.2742061
X. Zhang, M. Tehranipoor, Case study: detecting hardware trojans in third-party digital ip cores, in Hardware-Oriented Security and Trust (HOST), 2011 IEEE International Symposium, June (2011), pp. 67–70
S. Bhunia, M. Abramovici, D. Agrawal, P. Bradley, M. Hsiao, J. Plusquellic, M. Tehranipoor, Protection against hardware trojan attacks: towards a comprehensive solution. Design Test, IEEE 30(3), 6–17, June (2013)
F. Hategekimana, A. Tbatou, C. Bobda, C.A. Kamhoua, K.A. Kwiat, Hardware isolation technique for irc-based botnets detection, in International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015 (Riviera Maya, Mexico, December 7–9, 2015), pp. 1-6. http://dx.doi.org/10.1109/ReConFig.2015.7393319
ARM: Trust zone January (2015). http://www.arm.com/products/processors/technologies/trustzone/
W. Venema, Isolation mechanisms for commodity applications and platforms. Tech. Rep. RC24725(W0901–048), IBM (01 2009)
A. Pnueli, Special issue semantics of concurrent computation the temporal semantics of concurrent programs. Theor. Comput. Sci. 13(1), 45–60 (1981). http://www.sciencedirect.com/science/article/pii/0304397581901109
Z. Glazberg, M. Moulin, A. Orni, S. Ruah, E. Zarpas, Psl: Beyond hardware verification, in S. Ramesh, P. Sampath P (eds.) Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems, pp. 245–260 (Springer, Netherlands, 2007). http://dx.doi.org/10.1007/978-1-4020-6254-4_19
M.C. Stamm, I. Savidis, B. Taskin, Securing Integrated Circuits Against Hardware Trojans Using Information Forensics. - Dept. of Electrical and Computer Engineering, Drexel University
M.C. Stamm, W.S. Lin, K.J.R. Liu, Forensics vs. anti-forensics: a decision and game theoretic framework, in IEEE International Conference on Acoustic, Speech, and Signal Processing (ICASSP) (Kyoto, Japan, March 2012), pp. 1749–1759
M.C. Stamm, M. Wu, K.J. Liu. Information forensics: an overview of the first decade. IEEE Acc. 1, 167—200 (2013)
R. Rad, J. Plusquellic, M. Tehranipoor, A sensitivity analysis of power signal methods for detecting hardware trojans under real process and environmental conditions. IEEE Trans. VLSI (TVLSI) 18(2), 1735–1744, December (2010)
D. Komolov, Using special memory microcircuits to ensure FPGA protection from copying. Comp. Technol, 12 (2008)
A. Kolossov, R. Zolotukha, A study of special memory microcircuits to ensure FPGA protection from copying. www.maxim-ic.com/DS28E01
F. Koushanfar, Integrated Circuits Metering for Piracy Protection and Digital Rights Management: An Overview (Electrical and Computer Engineering Rice University, Houston, TX)
Y. Alkabani, F. Koushanfar, N. Kiyavash, M. Potkonjak. Trusted integrated circuits: a nondestructive hidden characteristics extraction approach, in IH (2008), pp. 102—117
B. Barak, O. Goldreich, R. Impagliazzo, S. Rudich, A. Sahai, S. Vadhan, K. Yang, On the (im)possibility of obfuscating programs, in CRYPTO (2001), pp. 1—18
A. Baumgarten, A. Tyagi, J. Zambreno, Preventing IC piracy using reconfigurable logic barriers. IEEE Des. Test Comput. 27, 66—75 (2010)
R. Chakraborty, S. Bhunia, Hardware protection and authentication through netlist level obfuscation, in ICCAD (2008), pp. 674–677
S. Devadas, B. Gassend, Authentication of integrated circuits. US Patent 7,840,803 (2010)
B. Gassend, D. Clarke, M. van Dijk, S. Devadas, Silicon physical random functions, in CCS (2002), pp. 148–160
D. Holcomb, W Burleson, K. Fu, Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans. Comput. 58(9), 1198–1210, September (2009)
J. Huang, J. Lach, IC activation and user authentication for security-sensitive systems, in HOST (2008), pp. 76–80
F. Koushanfar, Active integrated circuits metering techniques for piracy avoidance and digital rights management, in Technical Report TREE1101, ECE Dept., Rice University (2011)
F. Koushanfar, Book Chapter, in Introduction to Hardware Security and Trust, M. Tehranipoor, C. Wang (eds.), Chapter Hardware metering (A survey. Springer, 2011)
F. Koushanfar, G. Qu, Hardware metering, in Design Automation Conference, DAC (2001), pp. 490–493
F. Koushanfar, G. Qu, M, Potkonjak. Intellectual property metering, in IH (2001), pp. 81–95
K. Lofstrom, W.R. Daasch, D. Taylor, Ic identification circuit using device mismatch, in ISSCC (2000), pp. 372–373
R. Maes, D. Schellekens, P Tuyls, I. Verbauwhede, Analysis and design of active IC metering schemes, in HOST (2009), pp. 74–81
C. Mouli, W. Carriker, Future fab: how software is helping intel go nano-and beyond, in IEEE Spectrum, March (2007)
J. Roy, F. Koushanfar, I. Markov, Protecting bus-based hardware ip by secret sharing, in DAC (2008), pp. 846–851
J. Roy, F. Koushanfar, I. Markov, EPIC: ending piracy of integrated circuits, in DATE (2008), pp. 1069–1074
J. Roy, F. Koushanfar, I. Markov, Ending piracy of integrated circuits. IEEE Comput. 43, 30–38 (2008)
U. Rtihrmair, S. Devadas, F. Koushanfar, Book Chapter, in Introduction to Hardware Security and Trust, M. Tehranipoor, C. Wang (eds.), Chapter Security based on Physical Unclonability and Disorder. Springer (2011)
B. Santo, Plans for next-gen chips imperile, in IEEE Spectrum, August (2007)
L. Yuan, G. Qu, Information hiding in finite state machine, in IH (2004), pp. 340–354
A. Baumgarten, M. Steffen, M. Clausman, J. Zambreno, A case study in hardware Trojan design and implementation. Int. J. Inf. Sec. 10, 1–14 (2010)
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Belous, A., Saladukha, V. (2020). Countermeasures Against Hardware Trojans. In: Viruses, Hardware and Software Trojans. Springer, Cham. https://doi.org/10.1007/978-3-030-47218-4_7
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