Practical Evaluation Methodology of Higher-Order Maskings at Different Operating Frequencies

Abstract

FPGA is widely used in the cryptographic devices, such as security co-processor and crypto engine, due to its high speed and customizability. Side-channel analysis is the state-of-the-art method which could recover the secret information in the FPGA through measuring and analysing the power consumption or the electromagnetic radiation. Therefore, side-channel analysis may lead to a potential threat of the security of FPGA. We find that an excessively high operating frequency could cause a pretty serious security vulnerability in the FPGA implementation of a cryptographic algorithm with side-channel countermeasures. And then, how to evaluate the security of the implementation at different operating frequencies is an important question in the practical application. After investigating the physical reason of the information leakage of the FPGA, we propose a generic evaluation methodology derived from CPA and MIA that can be utilized to analyze the security of FPGA implementation of a cryptographic algorithm with side-channel countermeasures at different operating frequencies. By this methodology, the evaluator only needs to collect the measurements when the FPGA operates at an arbitrary frequency rather than collecting the measurement of all possible frequencies exhaustively. Finally, several experiments in an FPGA with AES cryptographic algorithm protected with a masking countermeasure are conducted to illustrate the feasibility of this methodology.